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EM78P341/2/3N
8-Bit Microprocessor with OTP ROM
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
December 2006
Contents
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, TAIWAN 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (U.S.A.) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 U.S.A. Tel: +1 408 366-8225 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 3 4 5 General Description ................................................................................................ 3 Features ................................................................................................................... 3 Pin Assignment ....................................................................................................... 4 Functional Block Diagram ...................................................................................... 5 Pin Description........................................................................................................ 6 5.1 5.2 6 EM78P341NP/M............................................................................................... 6 EM78P342NP/M............................................................................................... 7
5.3 EM78P343NP/M/KM......................................................................................... 8 Function Description .............................................................................................. 9 6.1 Operational Registers ....................................................................................... 9
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 R0 (Indirect Address Register) .......................................................................... 9 R1 (Time Clock /Counter) ................................................................................... 9 R2 (Program Counter) and Stack ....................................................................... 9 6.1.3.1 Data Memory Configuration................................................................11 R3 (Status Register) ......................................................................................... 12 R4 (RAM Select Register) ................................................................................ 12 R5 ~ R6 (Port 5 ~ Port 6).................................................................................. 13 R7 (Port 7) ........................................................................................................ 13 R8 (AISR: ADC Input Select Register) ............................................................. 14 R9 (ADCON: ADC Control Register) ................................................................ 15 RA (ADOC: ADC Offset Calibration Register) .................................................. 17 RB (ADDATA: Converted Value of ADC) .......................................................... 17 RC (ADDATA1H: Converted Value of ADC) ..................................................... 17 RD (ADDATA1L: Converted Value of ADC) ...................................................... 18 RE (Interrupt Status 2 & Wake-up Control Register) ........................................ 18 RF (Interrupt Status 2 Register)........................................................................ 19 R10 ~ R3F ........................................................................................................ 19 A (Accumulator) ................................................................................................ 20 CONT (Control Register) .................................................................................. 20 IOC50 ~ IOC70 (I/O Port Control Register)...................................................... 21 IOC80 (Comparator and TCCA Control Register) ............................................ 21 IOC90 (TCCB and TCCC Control Register) ..................................................... 22 IOCA0 (IR and TCCC Scale Control Register)................................................. 23 IOCB0 (Pull-Down Control Register) ................................................................ 24 IOCC0 (Open-Drain Control Register) ............................................................. 24 IOCD0 (Pull-high Control Register) .................................................................. 25
6.2
Special Purpose Registers.............................................................................. 20
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9
Product Specification (V1.0) 12.01.2006
*iii
Contents
6.2.10 6.2.11 6.2.12 6.2.13 6.2.14 6.2.15 6.2.16 6.2.17 6.2.18 6.2.19 6.2.20 6.2.21 6.2.21
IOCE0 (WDT Control & Interrupt Mask Registers 2) ........................................ 25 IOCF0 (Interrupt Mask Register) ...................................................................... 26 IOC51 (TCCA Counter) .................................................................................... 27 IOC61 (TCCB Counter) .................................................................................... 28 IOC71 (TCCBH/MSB Counter)......................................................................... 28 IOC81 (TCCC Counter) .................................................................................... 28 IOC91 (Low-Time Register).............................................................................. 29 IOCA1 (High Time Register)............................................................................. 29 IOCB1 High/Low Time Scale Control Register)................................................ 29 IOCC1 (TCC Prescaler Counter)...................................................................... 30 IOCD1 (LVD Control Register) ......................................................................... 31 IOCE1 (Output Sink Select Control Register) .................................................. 32 IOCF1 (Pull-high Control Register)................................................................... 33
6.3 6.4 6.5
TCC/WDT and Prescaler ................................................................................ 33 I/O Ports ......................................................................................................... 35
6.4.1 6.5.1 Usage of Port 5 Input Change Wake-up/Interrupt Function ............................. 37 Reset and Wake-up Operation ......................................................................... 37 6.5.1.1 Wake-up and Interrupt Modes Operation Summary.......................... 40 6.5.1.2 Register Initial Values after Reset ..................................................... 46 6.5.1.3 Controller Reset Block Diagram ........................................................ 51 The T and P Status under Status (R3) Register ............................................... 51
Reset and Wake-up ........................................................................................ 37
6.5.2
6.6 6.7
Interrupt .......................................................................................................... 52 Analog-To-Digital Converter (ADC) ................................................................. 55
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)............................... 55 6.7.1.1 R8 (AISR: ADC Input Select Register) .............................................. 55 6.7.1.2 R9 (ADCON: AD Control Register).................................................... 56 6.7.1.3 RA (ADOC: AD Offset Calibration Register) ...................................... 57 ADC Sampling Time ......................................................................................... 58 AD Conversion Time......................................................................................... 58 ADC Operation during Sleep Mode .................................................................. 59 Programming Process/Considerations ............................................................. 59 6.7.6.1 Programming Process ....................................................................... 59 6.7.6.2 Sample Demo Programs ................................................................... 60 Overview........................................................................................................... 62 Function Description ......................................................................................... 63 Programming the Related Registers ............................................................... 65 Overview........................................................................................................... 66 Function Description ......................................................................................... 66 Programming the Related Registers ................................................................ 68
6.7.3 6.7.4 6.7.5 6.7.6
6.8
Infrared Remote Control Application/PWM Waveform Generation .................. 62
6.8.1 6.8.2 6.8.3
6.9
Timer/Counter................................................................................................. 66
6.9.1 6.9.2 6.9.3
iv *
Product Specification (V1.0) 12.01.2006
Contents
6.10 Comparator..................................................................................................... 68
6.10.1 6.10.2 6.10.3 6.10.4 6.10.5 6.11.1 6.11.2 6.11.3 6.11.4 External Reference Signal................................................................................ 69 Comparator Outputs ......................................................................................... 69 Using a Comparator as an Operation Amplifier ................................................ 70 Comparator Interrupt ........................................................................................ 70 Wake-up from Sleep Mode ............................................................................... 70 Oscillator Modes ............................................................................................... 71 Crystal Oscillator/Ceramic Resonators (Crystal) .............................................. 71 External RC Oscillator Mode ............................................................................ 73 Internal RC Oscillator Mode ............................................................................. 74
6.11 Oscillator ........................................................................................................ 71
6.12 Power-on Considerations................................................................................ 75
6.12.1 Programmable WDT Time-out Period .............................................................. 75 6.12.2 External Power-on Reset Circuit ...................................................................... 75 6.12.3 Residual Voltage Protection ............................................................................. 76
6.13 Code Option ................................................................................................... 77
6.13.1 Code Option Register (Word 0) ........................................................................ 77 6.13.2 Code Option Register (Word 1) ........................................................................ 78 6.13.3 Customer ID Register (Word 2) ........................................................................ 79
6.14 Low Voltage Detector...................................................................................... 80
6.14.1 Low Voltage Reset............................................................................................ 80 6.14.2 Low Voltage Detector........................................................................................ 80 6.14.2.1 IOCD1 (LVD Control Register) .......................................................... 80 6.14.2.2 RE (Interrupt Status 2 & Wake-up Control Register) ......................... 81 6.14.3 Programming Process ...................................................................................... 82
6.15 Instruction Set................................................................................................. 83 7 8 Absolute Maximum Ratings.................................................................................. 85 DC Electrical Characteristics................................................................................ 85 8.1 8.2 8.3 9 10 AD Converter Characteristics ......................................................................... 86 Comparator (OP) Characteristics.................................................................... 87 Device Characteristics .................................................................................... 88
AC Electrical Characteristic.................................................................................. 89 Timing Diagrams ................................................................................................... 90
Product Specification (V1.0) 12.01.2006
*v
Contents
APPENDIX
A. B Package Type ........................................................................................................ 91 Packaging Configuration ...................................................................................... 91 B.1 14-Lead Plastic Dual in line (PDIP) -- 300 mil ................................................ 91 B.2 14-Lead Plastic Small Outline (SOP) -- 150 mil ............................................. 92 B.3 18-Lead Plastic Dual in line (PDIP) -- 300 mil ................................................ 91 B.4 18-Lead Plastic Small Outline (SOP) -- 300 mil ............................................. 92 B.5 20-Lead Plastic Shrink Small Outline (SSOP) -- 209 mil................................ 93 B.6 20-Lead Plastic Dual-in-line (PDIP) -- 300 mil................................................ 94 C B.7 20-Lead Plastic Small Outline (SOPP) -- 300 mil........................................... 95 Quality Assurance and Reliability ........................................................................ 96 C.1 Address Trap Detect ....................................................................................... 96
Specification Revision History
Specification Revision History Doc. Version 1.0 Initial released version Revision Description Date 2006/12/01
vi *
Product Specification (V1.0) 12.01.2006
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
1
General Description
The EM78P341N, EM78P342N and EM78P343N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. The series have an on-chip 2Kx13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user's OTP memory code. Three Code option bits are also available to meet user's requirements. With enhanced OTP-ROM features, the EM78P341N, EM78P342N and EM78P343N provide a convenient way of developing and verifying user's programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.
2
* * * * * * * * * * * * * * * * * * *
Features
CPU configuration 2Kx13 bits on chip ROM 80x8 bits on chip registers (SRAM) 8 level stacks for subroutine nesting 4 programmable Level Voltage Detector (LVD) : 4.5V, 4.0V, 3.3V, 2.2V 4 programmable Level Voltage Reset (LVR) : 4.0V, 3.5V, 2.7V, 1.8V (POR) Less than 1.5 mA at 5V/4MHz Typically 15 A, at 3V/32kHz Typically 1 A, during sleep mode Three bidirectional I/O ports : P5, P6, P7 18 I/O pins Wake-up port : P5 8 Programmable pull-down I/O pins 16 programmable pull-high I/O pins 8 Programmable open-drain I/O pins External interrupt : P60 Commercial version: Operating voltage range 1.9V~5.5V Industrial version: Operating voltage range: 2.1V~5.5V Commercial version: Operating voltage range: 0C ~ 70C Industrial version: Operating voltage range: -40C ~ 85C
*
IRC mode: Oscillation mode : 4MHz, 16MHz, 1MHz, 455kHz Process deviation : Typ3%, Max5% Temperature deviation : 10% (-40C~85C ) Easily implemented IR (or infrared remote control) 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt 8-bit real time clock/counter (TCCA, TCCC) and 16-bit real time clock/counter (TCCB) with selective signal sources, trigger edges, and overflow interrupt 8-bit channels Analog-to-Digital Converter with 12-bit resolution One pair of comparators or OP TCC, TCCA, TCCB, TCCC overflow interrupt Input-port status changed interrupt (wake-up from sleep mode) External interrupt ADC completion interrupt IR/PWM interrupt Comparator status change interrupt Low voltage detect (LVD) interrupt Programmable free running watchdog timer (4.5ms:18ms) Power saving Sleep mode Selectable Oscillation mode Power-on voltage detector available (1.7 V 0.1V) 14-pin DIP 300mil 14-pin SOP 150mil 18-pin DIP 300mil 18-pin SOP 300mil 20-pin DIP 300mil 20-pin SOP 300mil 20-pin SSOP 209mil : : : : : : : EM78P341NP EM78P341NM EM78P342NP EM78P342NM EM78P343NP EM78P343NM EM78P343NKM
Peripheral configuration
* * * * * * * * * * * * * * * * * * * * * * *
I/O port configuration
Seven available interrupts:
Operating voltage range:
Special features
Operating temperature range: -40~85C
Package type:
* *
Operating frequency range: Main clock Crystal mode: DC ~ 20MHz/2clks @ 4V; DC ~16 MHz/2clks @ 3V DC ~ 4MHz/2clks @ 1.9V ERC mode: DC ~ 4MHz/2clks @ 5V; DC ~ 4MHz/2clks @ 3V DC ~ 8MHz/2clks @ 3V; DC ~ 250ns inst. cycle @ 3V
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
*1
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
3 Pin Assignment
(1) 14-Pin DIP/SOP (2) 18-Pin DIP/SOP
P52/ADC2
1 2 3 EM78P342NP EM78P342NM 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
P51/ADC1 P50/ADC0 P55/OSCI/ADC6 P70/OSCO/ADC5 VDD P67/IR OUT/ADC4 P66/CINP65/CIN+ P64/CO
P52/ADC2 P53/ADC3 P54/TCC/VREF /RESET Vss P60//INT P61/TCCA
1 2 3 4 5 6 7 EM78P341NP EM78P341NM
14 13 12 11 10 9 8
P51/ADC1 P50/ADC0 P55/OSCI/ADC6 P70/OSCO/ADC5 VDD P67/IR OUT/ADC4 P66/CIN-
P53/ADC3 P54/TCC/VREF /RESET Vss P60//INT P61/TCCA P62/TCCB P63/TCCC
Fig. 3-1 14-pin EM78P341NP/NM
Fig. 3-2 18-pin EM78P342NP/NM
(3)
20-Pin DIP/SOP/SSOP
P56 P52/ADC2 P53/ADC3 P54/TCC/VREF /RESET Vss P60//INT P61/TCCA P62/TCCB P63/TCCC
1 2 3 4 5 6 7 8 9 10 EM78P343N
20 19 18 17 16 15 14 13 12 11
P57/ADC7 P51/ADC1 P50/ADC0 P55/OSCI/ADC6 P70/OSCO/ADC5 VDD P67/IR OUT/ADC4 P66/CINP65/CIN+ P64/CO
Fig. 3-3 20-pin EM78P343NP/NM/NKM
2*
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
4 Functional Block Diagram
Ext. OSC. Int. RC Ext. RC
ROM
PC
Start-up timer WDT
Instruction Register
P70 P71
8-level stack (13 bit)
Oscillation Generation
TCCA TCCB
TCCA TCCB TCCC
Instruction Decoder
Reset
TCCC Infrared remote control circuit
IR out
P6
P60 P61 P62 P63 P64 P65 P66 P67
Mux ALU
TCC
TCC
R4 LVD RAM
P5
P50 P51 P52 P53 P54 P55 P56 P57
ACC
R3 (Status Reg.)
Interrupt control register
LVR
Interrupt circuit
ADC
Comparator (CO) or OP
Ext INT
Ain0~3
Cin+ Cin- CO
Fig. 4-1 EM78P341N/342N/343N Functional Block Diagram
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
*3
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
5
Pin Description
5.1 EM78P341NP/M
Symbol Pin No. Type Function 6-bit General purpose input/output pins Pull-high/pull-down Wake up from sleep mode when the pin status changes Default value at power-on reset 4-bit General purpose input/output pins Open drain Default value at power-on reset 2-bit General purpose input/output pins Default value at power-on reset External interrupt pin triggered by a falling or a rising edge. Defined by CONT <7> 7-bit Analog-to-Digital Converter Defined by ADCON (R9)<1:0> External reference voltage for ADC Defined by ADCON (R9) <7>. General-purpose Input only If it remains at logic low, the device will be reset Wake-up from sleep mode when pin status changes Voltage on /RESET must not exceed Vdd during normal mode External Counter input TCC defined by CONT<5> TCCA defined by IOC80 <1> Crystal type: Crystal input terminal or external clock input pin RC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator or external clock input pin. RC type: Clock output with a duration of one instruction cycle time. The prescaler is determined by the CONT register. External clock signal input. IR mode output pin. Driving current = 10mA when the output voltage drops to Vdd-0.5V at Vdd = 5V Sinking current = 15mA when the output voltage drops to GND+0.5V at Vdd = 5V Power supply Ground
P50~P55
1~3, 12~14
I/O
P60, P61 66, 67 P70~P71 /INT ADC0~ADC6 VREF
6~9
I/O
11, 4 6 1, 2, 9 11~14 3
I/O I I I
/RESET
4
I
TCC, TCCA
3, 7
I
OSCI
12
I
OSCO
11
O
IR OUT
13
O
VDD VSS
10 5
- -
4*
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
5.2 EM78P342NP/M
Symbol Pin No. Type Function 6-bit General purpose input/output pins Pull-high/pull-down Wake up from sleep mode when the pin status changes Default value at power-on reset 8-bit General purpose input/output pins Open drain Default value at power-on reset 2-bit General purpose input/output pins Default value at power-on reset External interrupt pin triggered by a falling or a rising edge. Defined by CONT <7> 7-bit Analog-to-Digital Converter Defined by ADCON (R9)<1:0> External reference voltage for ADC Defined by ADCON (R9) <7>. "-" : the input pin of Vin- of the comparator "+" : the input pin of Vin+ of the comparator Pin CO is the comparator output Defined by IOC80 <4:3> General-purpose Input only If it remains at logic low, the device will be reset Wake-up from sleep mode when pin status changes Voltage on /RESET must not exceed Vdd during normal mode External Counter input TCC defined by CONT<5> TCCA defined by IOC80 <1> TCCB defined by IOC90 <5> TCCC defined by IOC90 <1> Crystal type: Crystal input terminal or external clock input pin RC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator or external clock input pin. RC type: Clock output with a duration of one instruction cycle time. The prescaler is determined by the CONT register. External clock signal input. IR mode output pin. Capable of driving and sinking current = 20mA when the output voltage drops to 0.7Vdd at rise to 0.3Vdd at Vdd = 5V Power supply Ground
P50~P55
1~3, 16~18
I/O
P60~67
6~13
I/O
P70~P71 /INT ADC0~ADC6 VREF CINCIN+ CO
15, 4 6 1, 2, 13 15~18 3 12 11 10
I/O I I I I I O
/RESET
4
I
TCC, TCCA TCCB, TCCC
3, 7 8~9
I
OSCI
16
I
OSCO
15
O
IR OUT
13 14 5
O
VDD VSS
- -
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
*5
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
5.3 EM78P343NP/M/KM
Symbol Pin No. Type Function 8-bit General purpose input/output pins Pull-high/pull-down Wake up from sleep mode when the pin status changes Default value at power-on reset 8-bit General purpose input/output pins Open drain Default value at power-on reset 2-bit General purpose input/output pins Default value at power-on reset External interrupt pin triggered by a falling or a rising edge. Defined by CONT <7> 8-bit Analog-to-Digital Converter Defined by ADCON (R9) <2:0> External reference voltage for ADC Defined by ADCON (R9) <7>. "-" : the input pin of Vin- of the comparator "+" : the input pin of Vin+ of the comparator Pin CO is the comparator output Defined by IOC80 <4:3> General-purpose Input only If it remains at logic low, the device will be reset Wake-up from sleep mode when pin status changes Voltage on /RESET must not exceed Vdd during normal mode External Counter input TCC defined by CONT<5> TCCA defined by IOC80 <1> TCCB defined by IOC90 <5> TCCC defined by IOC90 <1> Crystal type: Crystal input terminal or external clock input pin RC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator or external clock input pin. RC type: Clock output with a duration of one instruction cycle time. The prescaler is determined by the CONT register. External clock signal input. IR mode output pin. Capable of driving and sinking current = 20mA when the output voltage drops to 0.7Vdd at rise to 0.3Vdd at Vdd = 5V Power supply Ground
P50~P57
1~4, 17~20
I/O
P60~67
7~14
I/O
P70~P71 /INT ADC0~ADC7 VREF CINCIN+ CO
16, 5 7 2, 3, 14 16~20 4 13 12 11
I/O I I I I I O
/RESET
5
I
TCC, TCCA TCCB, TCCC
4, 8 9~10
I
OSCI
17
I
OSCO
16
O
IR OUT
14 15 6
O
VDD VSS
- -
6*
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6
Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4).
6.1.2 R1 (Time Clock /Counter)
Incremented by an external signal edge which is defined by the TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. Writable and readable as any other registers The TCC prescaler counter (IOCC1) is assigned to TCC The contents of the IOCC1 register is cleared whenever -
* a value is written to the TCC register. * a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of the CONT register) * there is power-on reset, /RESET, or WDT time out reset. 6.1.3 R2 (Program Counter) and Stack
R3
Reset Vector Hardware Interrupt Vector 021H 000H 003H
A10
A9 A8
A7 CALL RET RETL RETI
~
A0
User Memory Space
00 PAGE0 0000~03FF 01 PAGE1 0400~07FF
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 Stack Level 6 Stack Level 7 Stack Level 8
On-chip Program Memory
3FEH
7FFH
Fig. 6-1 Program Counter Organization
R2 and hardware stacks are 11-bit wide. The structure is depicted in the table under Section 6.1.3.1, Data Memory Configuration (next page). Generates 2Kx13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. The contents of R2 are all set to "0"s when a RESET condition occurs.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
*7
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged. Any instruction (except "ADD R2,A") that is written to R2 (e.g., "MOV R2, A", "BC R2, 6",) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged. In the case of EM78P341N/342N/343N, the most significant bit (A10) will be loaded with the content of PS0 in the status register (R3) upon execution of a "JMP", "CALL", or any other instructions set which write to R2. All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions that are written to R2. Note that these instructions need one or two instructions cycle as determined by Code Option Register CYES bit.
8*
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM 6.1.3.1 Data Memory Configuration
Address R Page Registers IOCX0 Page Registers IOCX1 Page Registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
R0 (Indirect Addressing Register) R1 (Timer Clock Counter) R2 (Program Counter) R3 (Status Register) R4 (RAM Select Register) R5 (Port 5) R6 (Port 6) R7 (Port 7) R8 (ADC Input Select Register R9 (ADC Control Register) RA (ADC Offset Calibration Register) (Converted value RB AD11~AD4 of ADC) RC (Converted value AD11~AD8 of ADC) (Converted value RD AD7~AD0 of ADC) RE (Interrupt Status 2 and Wake-up Control Register RF (Interrupt Status Register 1)
Reserve Reserve Reserve Reserve Reserve IOC50 (I/O Port Control Register) IOC60 (I/O Port Control Register) IOC70 (I/O Port Control Register) IOC80 IOC90 IOCA0 IOCB0 IOCC0 (Comparator and TCCA Control Register) (TCCB and TCCC Control Register) (IR and TCCC Scale Control Register) (Pull-down Control Register) (Open-drain Control Register)
Reserve Reserve Reserve Reserve Reserve IOC51 (TCCA Counter) IOC61 (TCCB LSB Counter) IOC71 (TCCB HSB Counter) IOC81 (TCCC Counter) IOC91 (Low-Time Register) IOCA1 (High-Time Register) IOCB1 (High-Time and Low-Time Scale Control Register)
IOCC1 (TCC Prescaler Control)
IOCD0 (Pull-high Control Register) IOCD1 (LVD Control Register) IOCE0 (WDT Control Register and Interrupt Mask Register 2) IOCF0 (Interrupt Mask Register 1) IOCE1 (High Output Sink Current) IOCF1 (Pull-high Control Register)
General Registers 1F 20 3F
Bank 0
Bank 1
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
*9
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.4 R3 (Status Register)
Bit 7 RST Bit 6 IOCS Bit 5 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 7 (RST): Bit of reset type Set to "1" if wake-up from sleep on pin change, comparator status change, or AD conversion completed. Set to "0" if wake-up from other reset types. Bit 6 (IOCS): Select the Segment of IO control register 0 = Segment 0 (IOC50 ~ IOCF0) selected 1 = Segment 1 (IOC51 ~ IOCC1) selected Bit 5: Bit 4 (T): Not used (reserved) Time-out bit. Set to "1" by the "SLEP" and "WDTC" commands or during power on, and reset to "0" by WDT time-out (see Section 6.5.2, The T and P Status under Status Register for more details). Bit 3 (P): Power-down bit. Set to "1" during power-on or by a "WDTC" command and reset to "0" by a "SLEP" command (see Section 6.5.2, The T and P Status under Status Register for more details). Bit 2 (Z): Bit 1 (DC): Bit 0 (C): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Auxiliary carry flag Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7: Bit 6: Bits 5~0: Set to "0" all the time Used to select Bank 0 or Bank 1 of register Used to select a register (address: 00~0F, 10~3F) in the indirect addressing mode See the table under Section 6.1.3.1, Data Memory Configuration.
10 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 & R6 are I/O registers The upper two bits of R5 are fixed to "0" (if EM78P342N is selected). Only the lower six bits of R5 are available (this applies to EM78P342N only since EM78P343N can use all the bits)
6.1.7 R7 (Port 7)
Bit EM78P342N/343N ICE342N 7 `0' C3 6 `0' C2 5 `0' C1 4 `0' C0 3 `0' RCM1 2 `0' RCM0 1 I/O I/O 0 I/O I/O
NOTE R7 is an I/O register For EM78P342N/343N, only the lower 2 bit of R7 is available.
Bit 7 ~ Bit 2: [With EM78P342N/343N]: Unimplemented, read as `0'. [With Simulator (C3~C0, RCM1, & RCM0)]: IRC calibration bits in IRC oscillator mode. In IRC oscillator mode of ICE342N simulator, these are the IRC mode selection bits and IRC calibration bits. Bit 7 ~ Bit 4 (C3 ~ C0): Calibrator of internal RC mode
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Frequency (MHz) (1-36%) x F (1-31.5%) x F (1-27%) x F (1-22.5%) x F (1-18%) x F (1-13.5%) x F (1-9%) x F (1-4.5%) x F F (default) (1+4.5%) x F (1+9%) x F (1+135%) x F (1+18%) x F (1+22.5%) x F (1+27%) x F (1+31.5%) x F
Note: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode.
Hence, they are shown for reference only. Definite values depend on the actual process. 2. Similar way of calculation is also applicable for low frequency mode.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 11
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 3 & Bit 2 (RCM1, RCM0):
RCM 1 1 1 0 0 RCM 0 1 0 1 0
IRC mode selection bits
Frequency (MHz) 4 (default) 16 1 455kHz
6.1.8 R8 (AISR: ADC Input Select Register)
The AISR register defines the I/O Port as analog inputs or as digital I/O, individually.
Bit 7 ADE7 Bit 6 ADE6 Bit 5 ADE5 Bit 4 ADE4 Bit 3 ADE3 Bit 2 ADE2 Bit 1 ADE1 Bit 0 ADE0
Bit 7 (ADE7): AD converter enable bit of P57 pin 0 = Disable ADC7, P57 functions as I/O pin 1 = Enable ADC7 to function as analog input pin Bit 6 (ADE6): AD converter enable bit of P55 pin 0 = Disable ADC6, P55 functions as I/O pin 1 = Enable ADC6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P70 pin 0 = Disable ADC5, P70 functions as I/O pin 1 = Enable ADC5 to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P67 pin 0 = Disable ADC4, P67 functions as I/O pin 1 = Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P53 pin 0 = Disable ADC3, P53 functions as I/O pin 1 = Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P52 pin 0 = Disable ADC2, P52 functions as I/O pin 1 = Enable ADC2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P51 pin 0 = Disable ADC1, P51 functions as I/O pin 1 = Enable ADC1 to function as analog input pin Bit 0 (ADE0): AD converter enable bit of P50 pin. 0 = Disable ADC0, P50 function as I/O pin 1 = Enable ADC0 to function as analog input pin
12 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE The P55/OSCI/ADC6 pin cannot be applied to OSCI and ADC6 at the same time. If P55/OSCI/ADC6 functions as OSCI oscillator input pin, then ADE6 bit for R8 must be "0" and ADIS2~0 do not select " 110". The P55/OSCI/ADC6 pin priority is as follows:
P55/OSCI/ADC6 Pin Priority
High OSCI Medium ADC6 Low P55
The P70/OSCO/ADC5 pin cannot be applied to OSCO and ADC5 at the same time. If P70/OSCO/ADC5 acts as OSCO oscillator input pin, then ADE5 bit for R8 must be "0" and ADIS2~0 do not select "101". The P70/OSCO/ADC5 pin priority is as follows:
P70/OSCO/ADC5 Pin Priority
High OSCO Medium ADC5 Low P70
The P66/IR OUT/ADC4 pin cannot be applied to IR OUT and ADC4 at the same time. If P67/IR OUT/ADC4 functions as ADC4 analog input pin, then IROUTE bit for IOCA0 must be "0".. If P67/IR OUT/ADC4 functions as IR OUT analog input pin, then ADE4 bit for R8 must be "0" and ADIS2~0 do not select "100". The P67/IR OUT/ADC4 pin priority is as follows:
P67/IR OUT/ADC4 Pin Priority
High ADC7 Medium IR OUT Low P67
6.1.9
Bit 7
R9 (ADCON: ADC Control Register)
Bit 6 CKR1 Bit 5 CKR0 Bit 4 ADRUN Bit 3 ADPD Bit 2 ADIS2 Bit 1 ADIS1 Bit 0 ADIS0
VREFS
Bit 7 (VREFS): The input source of the Vref of the ADC 0 = The Vref of the ADC is connected to Vdd (default value), and the VREF/TCC/P54 pin carries out the function of P54 1 = The Vref of the ADC is connected to VREF/TCC/P54
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 13
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P53/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 "TS" must be "0." The VREF/TCC/P54 Pin Priority is as follows: P53/TCC/VREF Pin Priority High VREF Medium TCC Low P54
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of ADC oscillator clock rate 00 = 1: 16 (default value) 01 = 1: 4 10 = 1: 64 11 = 1: 8
CPUS 1 1 1 1 0 CKR1:CKR0 00 01 10 11 XX Operation Mode Fosc/16 Fosc/4 Fosc/64 Fosc/8 Internal RC Max. Operation Frequency 4MHz 1MHz 16MHz 2MHz -
Bit 4 (ADRUN): ADC starts to RUN. 1 = an AD conversion is started. This bit can be set by software 0 = Reset upon completion of the conversion. This bit cannot be reset through software Bit 3 (ADPD): ADC Power-down mode 1 = ADC is operating 0 = Switch off the resistor reference to save power even while the CPU is operating Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select 000 = ADIN0/P50 001 = ADIN1/P51 010 = ADIN2/P52 011 = ADIN3/P53 100 = ADIN0/P67 101 = ADIN1/P70 110 = ADIN2/P55 111 = ADIN3/P57 These bits can only be changed when the ADIF bit (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) and the ADRUN bit are both LOW.
14 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.10 RA (ADOC: ADC Offset Calibration Register)
Bit 7 CALI Bit 6 SIGN Bit 5 VOF[2] Bit 4 VOF[1] Bit 3 VOF[0] Bit 2 "0" Bit 1 "0" Bit 0 "0"
Bit 7 (CALI):
Calibration enable bit for ADC offset 0 = Calibration disable 1 = Calibration enable
Bit 6 (SIGN):
Polarity bit of offset voltage 0 = Negative voltage 1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2] 0 0 0 0 1 1 1 1 VOF[1] 0 0 1 1 0 0 1 1 VOF[0] 0 1 0 1 0 1 0 1 EM78P342N/343N 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB ICE342N 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
Bit 2 ~ Bit 0:
Unimplemented, read as `0'
6.1.11 RB (ADDATA: Converted Value of ADC)
Bit 7 AD11 Bit 6 AD10 Bit 5 AD9 Bit 4 AD8 Bit 3 AD7 Bit 2 AD6 Bit 1 AD5 Bit 0 AD4
When the AD conversion is completed, the result is loaded into the ADDATA. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set. RB is read only.
6.1.12 RC (ADDATA1H: Converted Value of ADC)
Bit 7 "0" Bit 6 "0" Bit 5 "0" Bit 4 "0" Bit 3 AD11 Bit 2 AD10 1 AD9 0 AD8
When the AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-Up Control Register)) is set. RC is read only
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 15
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.13 RD (ADDATA1L: Converted Value of ADC)
Bit 7 AD7 Bit 6 AD6 Bit 5 AD5 Bit 4 AD4 Bit 3 AD3 Bit 2 AD2 Bit 1 AD1 Bit 0 AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set. RD is read only
6.1.14 RE (Interrupt Status 2 & Wake-up Control Register)
Bit 7 /LVD Bit 6 LVDIF Bit 5 ADIF Bit 4 CMPIF Bit 3 ADWE Bit 2 CMPWE Bit 1 ICWE Bit 0 LVDWE
NOTE RE <5,4> can be cleared by instruction but cannot be set. IOCE0 is the interrupt mask register. Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0 = low voltage is detected 1 = low voltage is not detected or LVD function is disabled
Bit 6 (LVDIF):
Low Voltage Detector interrupt flag LVDIF is reset to "0" by software. Interrupt flag for analog to digital conversion. Set when AD conversion is completed. Reset by software. 0 = no interrupt occurs 1 = interrupt request
Bit 5 (ADIF):
Bit 4 (CMPIF):
Comparator interrupt flag. Set when a change occurs in the Comparator output. Reset by software. 0 = no interrupt occurs 1 = interrupt request
Bit 3 (ADWE):
ADC wake-up enable bit 0 = Disable ADC wake-up 1 = Enable ADC wake-up When AD Conversion enters sleep mode, this bit must be set to "Enable".
16 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM Bit 2 (CMPWE): Comparator wake-up enable bit 0 = Disable Comparator wake-up 1 = Enable Comparator wake-up When Comparator enters sleep mode, this bit must be set to "Enable". Bit 1 (ICWE): Port 5 input change to wake-up status enable bit 0 = Disable Port 5 input change to wake-up status 1 = Enable Port 5 input change to wake-up status When Port 5 change enters sleep mode, this bit must be set to "Enable". Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit 0 = Disable Low Voltage Detect wake-up 1 = Enable Low Voltage Detect wake-up When the Low Voltage Detect is used to enter an interrupt vector or to wake-up the IC from sleep with Low Voltage Detect running, the LVDWE bit must be set to "Enable".
6.1.15 RF (Interrupt Status 2 Register)
Bit 7 LPWTIF Bit 6 HPWTIF Bit 5 TCCCIF Bit 4 TCCBIF Bit 3 TCCAIF Bit 2 EXIF Bit 1 ICIF Bit 0 TCIF
NOTE "1" means there is interrupt request; "0" means no interrupt occurs RF can be cleared by instruction but cannot be set. IOCF0 is the relative interrupt mask register. Reading RF will result to "logic AND" of RF and IOCF0.
Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software. Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software. Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by software. Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCC overflows. Reset by software. Bit 3 (TCCAIF): Bit 2 (EXIF): Bit 1 (ICIF): Bit 0 (TCIF): TCCA overflow interrupt flag. Set when TCCC overflows. Reset by software. External interrupt flag. Set by falling edge on /INT pin. Reset by software. Port 5 input status change interrupt flag. Set when Port 5 input changes. Reset by software. TCC overflow interrupt flag. Set when TCC overflows. Reset by software.
6.1.16 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2 Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator. The Accumulator is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7 INTE Bit 6 INT Bit 5 TS Bit 4 TE Bit 3 PSTE Bit 2 PST2 Bit 1 PST1 Bit 0 PST0
NOTE The CONT register is both readable and writable. Bit 6 is read only.
Bit 7 (INTE): INT signal edge 0 = interrupt occurs at a rising edge on the INT pin 1 = interrupt occurs at a falling edge on the INT pin Bit 6 (INT): Interrupt enable flag 0 = masked by DISI or hardware interrupt 1 = enabled by the ENI/RETI instructions This bit is readable only. Bit 5 (TS): TCC signal source 0 = internal instruction cycle clock. P54 is bi-directional I/O pin. 1 = transition on the TCC pin Bit 4 (TE): TCC signal edge 0 = increment if the transition from low to high takes place on the TCC pin 1 = increment if the transition from high to low takes place on the TCC pin. Bit 3 (PSTE): Prescaler enable bit for TCC 0 = prescaler disable bit. TCC rate is 1:1. 1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0. Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2 0 0 0 0 1 1 1 1 PST1 0 0 1 1 0 0 1 1 PST0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Note: Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)] Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)]
18 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
"1" sets the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. Only the lower six bits of IOC50 can be defined (this applies to EM78P341N/342N only since all bits of EM78P343N can be used). Only Bit 0, Bit 1, Bit 6, Bit 7 of IOC60 can be defined (this applies to EM78P341N only since all bits of EM78P343N can be used) Only the lower two bits of IOC70 can be defined, the others bits are not available. IOC50, IOC60, and IOC70 registers are all readable and writable
6.2.4 IOC80 (Comparator and TCCA Control Register)
Bit 7 - Bit 6 - Bit 5 CMPOUT Bit 4 COS1 Bit 3 COS0 Bit 2 TCCAEN Bit 1 TCCATS Bit 0 TCCATE
NOTE Bits 4 ~ 0 of the IOC80 register are both readable and writable EM78P341N cannot use the OP/comparator function Bit 5 of the IOC80 register is readable only.
Bit 7 & Bit 6: Not used Bit 5 (CMPOUT): Result of the comparator output. This bit is readable only. Bit 4 & Bit 3 (COS1 & COS0): Comparator/OP Select bits
COS1 0 0 1 1 COS0 0 1 0 1 Function Description Comparator and OP are not used. P64, P65, and P66 function as normal I/O pin Used as Comparator and P64 functions as normal I/O pin Used as Comparator and P64 functions as Comparator output pin (CO) Used as OP and P64 functions as OP output pin (CO)
Bit 2 (TCCAEN):
TCCA enable bit 0 = disable TCCA 1 = enable TCCA as a counter
Bit 1 (TCCATS):
TCCA signal source 0 =: internal instruction cycle clock. P61 is a bidirectional I/O pin. 1 = transit through the TCCA pin
Bit 0 (TCCATE):
TCCA signal edge 0 = increment if transition from low to high takes place on the TCCA pin 1 = increment if transition from high to low takes place on the TCCA pin
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 19
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.5 IOC90 (TCCB and TCCC Control Register)
Bit 7 TCCBHE Bit 6 TCCBEN Bit 5 TCCBTS Bit 4 TCCBTE Bit 3 - Bit 2 TCCCEN Bit 1 TCCCTS Bit 0 TCCCTE
NOTE The EM78P341N cannot define Bit 5, Bit 4, Bit 1, and Bit 0 of the IOC90.
Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of the counter 1 = Enable the most significant byte of TCCBH TCCB is a 16-bit counter. 0 = Disable the most significant byte of TCCBH (default value) TCCB is an 8-bit counter. Bit 6 (TCCBEN): TCCB enable bit 0 = disable TCCB 1 = enable TCCB as a counter Bit 5 (TCCBTS) TCCB signal source 0 = internal instruction cycle clock. P62 is a bi-directional I/O pin. 1 = transit through the TCCB/P62 pin Bit 4 (TCCBTE): TCCB signal edge 0 = increment if the transition from low to high takes place on the TCCB pin 1 = increment if the transition from high to low takes place on the TCCB pin Bit 3: Not used.
Bit 2 (TCCCEN): TCCC enable bit 0 = disable TCCC 1 = enable TCCC as a counter Bit 1 (TCCCTS) TCCC signal source 0 = internal instruction cycle clock. P63 is a bidirectional I/O pin. 1 = transit through the TCCC/P63 pin Bit 0 (TCCCTE): TCCC signal edge 0 = increment if the transition from low to high takes place on the TCCC pin 1 = increment if the transition from high to low takes place on the TCCC pin
20 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.6 IOCA0 (IR and TCCC Scale Control Register)
Bit 7 TCCCSE Bit 6 TCCCS2 Bit 5 TCCCS1 Bit 4 TCCCS0 Bit 3 IRE Bit 2 HF Bit 1 LGP Bit 0 IROUTE
Bit 7 (TCCCSE): Scale enable bit for TCCC An 8-bit counter is provided as scale for TCCC and IR-Mode. When in IR-Mode, TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). 0 = scale disable bit, TCCC rate is 1:1 1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4 Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to determine the scale ratio of TCCC as shown below:
TCCCS2 0 0 0 0 1 1 1 1 TCCCS1 0 0 1 1 0 0 1 1 TCCCS0 0 1 0 1 0 1 0 1 TCCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (IRE):
Infrared Remote Enable bit 0 = Disable IRE, i.e., disable H/W Modulator Function. The IROUT pin is fixed at a high level and the TCCC is an Up Counter. 1 = Enable IRE, i.e., enable H/W Modulator Function. Pin 67 is defined as IROUT. If HP=1, the TCCC counter scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). When HP=0, the TCCC is an Up Counter.
Bit 2 (HF):
High Frequency bit 0 = PWM application. IROUT waveform is achieved base on the high-pulse width timer and low-pulse width timer which determine the high time width and low time width respectively. 1 = IR application mode. The low-time segments of the pulse generated by the Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description)
Bit 1 (LGP):
Long Pulse. 0 = The high-time and low-time registers are valid 1 = The high-time register is ignored. A single pulse is generated.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 0 (IROUTE): Control bit used to define the P67 (IROUT) pin function 0 = P67 defined as bi-directional I/O pin 1 = P67 defined as IROUT. Under this condition, the I/O control bit of P67 (Bit 7 of IOC60) must be set to "0"
6.2.7 IOCB0 (Pull-Down Control Register)
Bit 7 /PD57 Bit 6 /PD56 Bit 5 /PD55 Bit 4 /PD54 Bit 3 /PD53 Bit 2 /PD52 Bit 1 /PD51 Bit 0 /PD50
NOTE IOCB0 register is both readable and writable
Bit 7 (/PD57): Control bit used to enable the pull-down function of the P57 pin (applicable to EM78P343N only) 0 = Enable internal pull-down 1 = Disable internal pull-down Bit 6 (/PD56): Control bit is used to enable the pull-down function of the P56 pin (applicable to EM78P343N only) Bit 5 (/PD55): Control bit used to enable the pull-down function of the P55 pin Bit 4 (/PD54): Control bit used to enable the pull-down function of the P54 pin Bit 3 (/PD53): Control bit used to enable the pull-down function of the P53 pin Bit 2 (/PD52): Control bit used to enable the pull-down function of the P52 pin Bit 1 (/PD51): Control bit used to enable the pull-down function of the P51 pin Bit 0 (/PD50): Control bit used to enable the pull-down function of the P50 pin.
6.2.8 IOCC0 (Open-Drain Control Register)
Bit 7 /OD67 Bit 6 /OD66 Bit 5 /OD65 Bit 4 /OD64 Bit 3 /OD63 Bit 2 /OD62 Bit 1 /OD61 Bit 0 /OD60
NOTE The IOCC0 register is both readable and writable.
Bit 7 (/OD67): Control bit is used to enable the open-drain output of the P67 pin 0 = Enable open-drain output 1 = Disable open-drain output Bit 6 (/OD66): Control bit used to enable the open-drain output of the P66 pin Bit 5 (/OD65): Control bit used to enable the open-drain output of the P65 pin (Not applicable to EM78P341N)
22 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 4 (/OD64): Control bit used to enable the open-drain of the P64 pin (Not applicable to EM78P341N) Bit 3 (/OD63): Control bit used to enable the open-drain of the P63 pin (Not applicable to EM78P341N) Bit 2 (/OD62): Control bit used to enable the open-drain of the P62 pin (Not applicable to EM78P341N) Bit 1 (/OD61): Control bit used to enable the open-drain of the P61 pin Bit 0 (/OD60): Control bit used to enable the open-drain of the P60 pin
6.2.9 IOCD0 (Pull-high Control Register)
Bit 7 /PH57 Bit 6 /PH56 Bit 5 /PH55 Bit 4 /PH54 Bit 3 /PH53 Bit 2 /PH52 Bit 1 /PH51 Bit 0 /PH50
NOTE The IOCD0 register is both readable and writable.
Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to EM78P343N only). 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 6 (/PH56): Control bit used to enable the pull-high function of the P56 pin (applicable to EM78P343N only). Bit 5 (/PH55): Control bit used to enable the pull-high function of the P55 pin. Bit 4 (/PH54): Control bit used to enable the pull-high function of the P54 pin. Bit 3 (/PH53): Control bit used to enable the pull-high function of the P53 pin. Bit 2 (/PH52): Control bit used to enable the pull-high function of the P52 pin. Bit 1 (/PH51): Control bit used to enable the pull-high function of the P51 pin. Bit 0 (/PH50): Control bit used to enable the pull-high function of the P50 pin.
6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2)
Bit 7 WDTE Bit 6 EIS Bit 5 ADIE Bit 4 CMPIE Bit 3 PSWE Bit 2 PSW2 Bit 1 PSW1 Bit 0 PSW0
Bit 7 (WDTE): Control bit used to enable Watchdog Timer 0 = Disable WDT 1 = Enable WDT WDTE is both readable and writable.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 23
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 6 (EIS):
Control bit used to define the function of the P60 (/INT) pin 0 = P60, bidirectional I/O pin 1 = /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC60) must be set to "1".
NOTE
When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 6-3 (I/O Port and I/O Control Register Circuit for P60 (/INT)) under Section 6.4 (I/O Ports). EIS is both readable and writable.
Bit 5 (ADIE):
ADIF interrupt enable bit 0 = disable ADIF interrupt 1 = enable ADIF interrupt
Bit 4 (CMPIE): CMPIF interrupt enable bit. 0 = disable CMPIF interrupt 1 = enable CMPIF interrupt Bit 3 (PSWE): Prescaler enable bit for WDT 0 = prescaler disable bit, WDT rate is 1:1 1 = prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0 Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2 0 0 0 0 1 1 1 1 PSW1 0 0 1 1 0 0 1 1 PSW0 0 1 0 1 0 1 0 1 WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
6.2.11 IOCF0 (Interrupt Mask Register)
Bit 7 LPWTIE Bit 6 HPWTIE Bit 5 TCCCIE Bit 4 TCCBIE Bit 3 TCCAIE Bit 2 EXIE Bit 1 ICIE Bit 0 TCIE
24 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE The IOCF0 register is both readable and writable. Individual interrupt is enabled by setting its associated control bit in the IOCF0 and in IOCE0 Bit 4 & 5 to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 6-7 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (LPWTIE): LPWTIF interrupt enable bit 0 = Disable LPWTIF interrupt 1 = Enable LPWTIF interrupt Bit 6 (HPWTIE): HPWTIF interrupt enable bit 0 = Disable HPWTIF interrupt 1 = Enable HPWTIF interrupt Bit 5 (TCCCIE): TCCCIF interrupt enable bit 0 = Disable TCCCIF interrupt 1 = Enable TCCCIF interrupt Bit 4 (TCCBIE): TCCBIF interrupt enable bit 0 = Disable TCCBIF interrupt 1 = Enable TCCBIF interrupt Bit 3 (TCCAIE): TCCAIF interrupt enable bit 0 = Disable TCCAIF interrupt 1 = Enable TCCAIF interrupt Bit 2 (EXIE): EXIF interrupt enable bit 0 = Disable EXIF interrupt 1 = Enable EXIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0 = Disable ICIF interrupt 1 = Enable ICIF interrupt Bit 0 (TCIE): TCIF interrupt enable bit. 0 = Disable TCIF interrupt 1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Counter)
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any reset condition and is an Up Counter.
NOTE TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)] TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2 (CLK=4)]
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 25
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.13 IOC61 (TCCB Counter)
IOC61 (TCCB) is an 8-bit clock counter for the least significant byte of TCCBX (TCCB). It can be read, written, and cleared on any reset condition and it is an Up Counter.
6.2.14 IOC71 (TCCBH/MSB Counter)
IOC71 (TCCBH/MSB) is an 8-bit clock counter for the most significant byte of TCCBX (TCCBH). It can be read, written, and cleared on any reset condition. When TCCBHE (IOC90) is "0," then TCCBH is disabled. When TCCBHE is"1," then TCCB is a 16-bit counter.
NOTE When TCCBH is Disabled: TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1 (CLK=2)] TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2 (CLK=4)] When TCCBH is Enabled: TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1 (CLK=2)} TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2 (CLK=4)}
6.2.15 IOC81 (TCCC Counter)
IOC81 (TCCC) is an 8-bit clock counter that can be extended to 16-bit counter. It can be read, written, and cleared on any reset condition. If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). Then TCCC value will be TCCC predicted value. When HP = 0 or IRE = 0, the TCCC is an UP Counter.
NOTE In TCCC Up Counter mode: TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1 (CLK=2)] TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2 (CLK=4)]
When HP = 1 and IRE = 1, TCCC counter scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation.
NOTE In IR mode: Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale (IOCA0) } FT is system clock: FT = Fosc/1 (CLK=2) FT = Fosc/2 (CLK=4)
26 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.16 IOC91 (Low-Time Register)
The 8-bit Low-time register controls the active or Low segment of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is active. The active period of IR OUT can be calculated as follows:
NOTE Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale (IOCB1) } / FT FT is system clock: FT = Fosc/1 (CLK=2) FT = Fosc/2 (CLK=4)
When an interrupt is generated by the Low time down counter underflow (if enabled), the next instruction will be fetched from address 015H (Low time).
6.2.17 IOCA1 (High Time Register)
The 8-bit High-time register controls the inactive or High period of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is inactive. The inactive period of IR OUT can be calculated as follows:
NOTE High time width = {[1+decimal high-time value (IOCA1)] * High time Scale (IOCB1) } / FT FT is system clock: FT=Fosc/1(CLK=2) FT=Fosc/2(CLK=4)
When an interrupt is generated by the High time down counter underflow (when enabled), the next instruction will be fetched from Address 012H (High time).
6.2.18 IOCB1 High/Low Time Scale Control Register)
Bit 7 HTSE Bit 6 HTS2 Bit 5 HTS1 Bit 4 HTS0 Bit 3 LTSE Bit 2 LTS2 Bit 1 LTS1 Bit 0 LTS0
Bit 7 (HTSE): High-time scale enable bit 0 = scale disable bit, High-time rate is 1:1 1 = scale enable bit, High-time rate is set as Bit 6~Bit 4.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 27
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High-time scale bits:
HTS2 0 0 0 0 1 1 1 1 HTS1 0 0 1 1 0 0 1 1 HTS0 0 1 0 1 0 1 0 1 High-time rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (LTSE): Low-time scale enable bit. 0 = scale disable bit, Low-time rate is 1:1 1 = scale enable bit, Low-time rate is set as Bit 2~Bit 0. Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low-time scale bits:
LTS2 0 0 0 0 1 1 1 1 LTS1 0 0 1 1 0 0 1 1 LTS0 0 1 0 1 0 1 0 1 Low-time Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
6.2.19 IOCC1 (TCC Prescaler Counter)
TCC prescaler counter can be read and written to:
PST2 PST1 PST0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 7 V Bit 6 V V Bit 5 V V V Bit 4 V V V V Bit 3 V V V V V Bit 2 V V V V V V Bit 1 V V V V V V V Bit 0 V V V V V V V V TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
V = valid value
The TCC prescaler counter is assigned to TCC (R1). The contents of the IOCC1 register are cleared when one of the following occurs: a value is written to TCC register a value is written to TCC prescaler bits (Bits 3, 2, 1, 0 of CONT) power-on reset, /RESET WDT time out reset
28 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.20 IOCD1 (LVD Control Register)
Bit EM78P342N/343N ICE342N 7 6 5 LVR1 4 LVR0 3 LVDIE LVDIE 2 LVDEN LVDEN 1 LVD1 LVD1 0 LVD0 LVD0
TYPE1 TYPE0
Bits 7~6 (Type 1 ~ Type 0): Type selection for EM78P343N or EM78P342N or EM78P341N or 108C.
Type 1, Type 0 11 10 01 00 VDD Reset Level EM78P343N (Default) (20PIN) EM78P342N (18PIN) EM78P341N (14PIN) 108C (8PIN)
Bits 5~4 (LVR1 ~ LVR0): Low Voltage Reset enable bits.
LVR1, LVR0 11 10 01 00 VDD Reset Level 2.7V 3.5V 4.0V NOTE IOCD1<3> register is both readable and writable Individual interrupt is enabled by setting its associated control bit in the IOCD1 <4> to "1" Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt). VDD Release Level 2.9V 3.7V 4.2V NA (Power-on Reset)
Bit 3 (LVDIE): Low voltage Detector interrupt enable bit. 0 = Disable Low voltage Detector interrupt. 1 = Enable Low voltage Detector interrupt. When the detect low level voltage is used to enter an interrupt vector or enter next instruction, the LVDIE bit must be set to "Enable". Bit 2 (LVDEN): Low Voltage Detector enable bit 0 = Low voltage detector disable 1 = Low voltage detector enable Bit 1~0 (LVD1:0): Low Voltage Detector level bits.
LVDEN 1 1 1 1 0 LVD1,LVD0 11 10 01 00 XX LVD voltage Interrupt level Vdd 2.3V Vdd > 2.3V Vdd 3.3V Vdd > 3.3V Vdd 4.0V Vdd > 4.0V Vdd 4.5V Vdd > 4.5V NA /LVD 0 1 0 1 0 1 0 1 0 * 29
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.21 IOCE1 (Output Sink Select Control Register)
Bit EM78P342N/343N ICE342N 7 6 5 4 IDLE IDLE 3 HS3 HS3 2 HS2 HS2 1 HS1 HS1 0 HS0 HS0 TIMERSC CPUS
WDTPS TIMERSC CPUS
Bit 7 (WDTPS):
WDT time-out period selection bit. 0 : 4.5ms 1 : 18ms
Bit 6 (TIMERSC): TCC, TCCA, TCCB, TCCC clock sources select 0/1 Fs/Fm* Fs: sub frequency for WDT internal RC time base Fm: main-oscillator clock Bit 5 (CPUS): CPU Oscillator Source Select, 0/1 sub-oscillator (fs) / main oscillator (fosc) When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped. Bit 4 (IDLE): Idle Mode Enable Bit. This bit will decide SLEP instruction which mode to go. 0 : Idle="0"+SLEP instruction sleep mode 1 : Idle="1"+SLEP instruction idle mode
Code option HLFS=1 Normal Mode external interrupt fosc:oscillation fs: oscillation CPU: using fosc wake up IDLE="0" +SLEP SLEEP Mode fosc:stop fs: stop CPU: stop IDLE="0" SLEP external interrupt CPUS="1" CPUS="0" IDLE="1 "+SLEP IDLE="1 "+SLEP IDLE Mode fosc:stop fs: oscillation wake up CPU: stop
CPU Operation Mode
RESET
Green Mode fosc:stop fs: oscillation CPU: using fs
Fig. 6-2 CPU Operation Mode
Bit 3 (HS3): Bit 2 (HS2): Bit 1 (HS1): Bit 0 (HS0):
Output Sink current Select for P63 (Not applicable for EM78P341N) Output Sink current Select for P62. (Not applicable for EM78P341N) Output Sink current Select for P61. Output Sink current Select for P60.
HSx 0 1 VDD = 5V, Sink Current 20mA (in 0.3VDD) 90mA (in 0.3VDD) Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
30 *
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.21 IOCF1 (Pull-high Control Register)
Bit 7 /PH67 Bit 6 /PH66 Bit 5 /PH65 Bit 4 /PH64 Bit 3 /PH63 Bit 2 /PH62 Bit 1 /PH61 Bit 0 /PH60
NOTE The IOCD0 register is both readable and writable.
Bit 7 (/PH67): Control bit is used to enable the pull-high of the P67 pin. 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 6 (/PH66): Control bit used to enable the pull-high function of the P66 pin. Bit 5 (/PH65): Control bit used to enable the pull-high function of the P65 pin. (Not applicable for EM78P341N) Bit 4 (/PH64): Control bit used to enable the pull-high function of the P64 pin. (Not applicable for EM78P341N) Bit 3 (/PH63): Control bit used to enable the pull-high function of the P63 pin. (Not applicable for EM78P341N) Bit 2 (/PH62): Control bit used to enable the pull-high function of the P62 pin. (Not applicable for EM78P341N) Bit 1 (/PH61): Control bit used to enable the pull-high function of the P61 pin. Bit 0 (/PH60): Control bit used to enable the pull-high function of the P60 pin.
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers that can be extended to 16-bit counter for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PWR2 ~ PWR0 bits of the IOCE0 register are used to determine the WDT prescaler. The prescaler counter is cleared by the instructions each time such instructions are written into TCC. The WDT and prescaler will be cleared by the "WDTC" and "SLEP" instructions. Fig. 6-1 (next page) depicts the block diagram of TCC/WDT. TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock or external signal input (edge selectable from the TCC pin). If TCC signal source is from an internal clock, TCC will be incremented by 1 at every instruction cycle (without prescaler). Referring to Fig. 6-1, CLK=Fosc/2 or CLK=Fosc/4 is dependent to the Code Option bit . CLK=Fosc/2 if the CLKS bit is "0," and CLK=Fosc/4 if the CLKS bit is "1." If the TCC signal source is from an external clock input, TCC will be incremented by 1 at every falling edge or rising edge of the TCC pin. The TCC pin input time length (kept at High or Low level) must be greater than 1CLK.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 31
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE The internal TCC will stop running when in sleep mode. However, during AD conversion, when TCC is set to "SLEP" instruction, if the ADWE bit of the RE register is enabled, TCC will keep on running.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). During normal operation or in sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2). With no prescaler, the WDT time-out period is approximately 18ms or 4.5ms .
CLK (Fosc/2 or Fosc/4) Data Bus 0 TCC Pin TE (CONT) 1 MUX 8 to 1 MUX Prescaler TS (CONT) PSR2~0 (CONT) 8-Bit Counter (IOCC1) SYNC 2 cycles TCC (R1)
1 2
TCC overflow interrupt
WDT
8-Bit Counter
8 to 1 MUX WDTE (IOCE0) WDT Time out
Prescaler
PSW2~0 (IOCE0)
Fig. 6-3 TCC and WDT Block Diagram
1
VDD=5V, WDT time-out period = 16.5ms 30% VDD=3V, WDT time-out period = 18ms 30% VDD=5V, WDT time-out period = 4.2ms 30% VDD=3V, WDT time-out period = 4.5ms 30% Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
2
32 *
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.4 I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain output set through software. Port 5 features an input status changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are illustrated in Figures 6-4, 6-5, 6-6, & 6-7 (see next page).
PCRD
Q _ Q
P R C L
D CLK PCWR
PORT
Q _ Q
P R C L
D CLK PDWR
IOD
PDRD 0 1 M U X
Note: Open-drain is not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for Port 6 and Port 7
PCRD
QPD R _ CLK QC L QPD R _ CLK QC L 0 1
PCWR
IOD PDWR
PORT Bit 6 of IOCE P DRQ CLK _ CQ L
M U X PDRD
INT
Note: Open-drain is not shown in the figure.
Fig. 6-5 I/O Port and I/O Control Register Circuit for P60 (/INT) Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 33
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
PCRD
Q Q
D
CLK
PCWR
P50 ~ P57
PORT Q Q D
CLK
IOD PDWR
0 1
M U X
PDRD TI n
D
CLK
Q Q
Note: Pull-high (down) is not shown in the figure.
Fig. 6-6 I/O Port and I/O Control Register Circuit for Port 50 ~ P57
I O C F.1
R F.1
TI 0 TI 1
TI 8
....
Fig. 6-7 Port 5 Block Diagram with Input Change Interrupt / Wake-up 34 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function
(1) Wake-up (a) Before Sleep 1. Disable WDT 2. Read I/O Port 5 (MOV R65R5) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction (b) After wake-up Next instruction (2) Wake-up and Interrupt (a) Before Sleep 1. Disable WDT 2. Read I/O Port 5 (MOV R5,R5) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Enable interrupt (Set IOCF ICIE =1) 6. Execute "SLEP" instruction (b) After wake-up 1. IF "ENI" Interrupt vector (008H) 2. IF "DISI" Next instruction (3) Interrupt (a) Before Port 5 pin change 1. Read I/O Port 6 (MOV R5,R5) 2. Execute "ENI" or "DISI" 3. Enable interrupt (Set IOCF ICIE =1) (b) After Port 5 pin changed (interrupt) 1. IF "ENI" Interrupt vector (006H) 2. IF "DISI" Next instruction
6.5 Reset and Wake-up
6.5.1 Reset and Wake-up Operation
A reset is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) The device is kept in reset condition for a period of approximately 18ms (except in LXT mode) after the reset is detected. When in LXT mode, the reset time is 500ms. Two choices (18ms or 4.5ms ) are available for WDT-time out period. Once a reset occurs, the following functions are performed (the initial address is 000h): The oscillator continues running, or will be started (if in sleep mode) The Program Counter (R2) is set to all "0"
3 4 3
3
VDD=5V, WDT Time-out period = 16.5ms 30%. VDD=3V, WDT Time-out period = 18ms 30%. VDD=5V, WDT Time-out period = 4.2ms 30%. VDD=3V, WDT Time-out period = 4.5ms 30%. * 35
4
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
All I/O port pins are configured as input mode (high-impedance state) The Watchdog Timer and prescaler are cleared When power is switched on, the upper three bits of R3 is cleared The IOCB0 register bits are set to all "1" The IOCC0 register bits are set to all "1" The IOCD0 register bits are set to all "1" Bits 7, 5, and 4 of the IOCE0 register are cleared Bits 5 and 4 of the RE register are cleared RF and IOCF0 registers are cleared Executing the "SLEP" instruction will assert the sleep (power down) mode. While entering into sleep mode, the Oscillator, TCC, TCCA, TCCB, and TCCC are stopped. The WDT (if enabled) is cleared but keeps on running. During AD conversion, when "SLEP" instruction is set; the Oscillator, TCC, TCCA, TCCB, and TCCC keep on running. The WDT (if enabled) is cleared but keeps on running. The controller can be awakened by: Case 1 Case 2 Case 3 Case 4 Case 5 Case 6 External reset input on /RESET pin WDT time-out (if enabled) Port 5 input status changes (if ICWE is enabled) Comparator output status changes (if CMPWE is enabled) AD conversion completed (if ADWE is enabled) Low Voltage Detector (if LVDWE is enabled)
The first two cases (1 & 2) will cause the EM78P341N/342N/343N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Cases 3, 4, & 5 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) determines whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from Address 0x06 (Case 3), 0x0F (Case 4), and 0x0C (Case 5) after wake-up. If DISI is executed before SLEP, the execution will restart from the instruction next to SLEP after wake-up. Only one of Cases 2 to 5 can be enabled before entering into sleep mode. That is: Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the EM78P341N/342N/343N can be awakened only with Case 1 or Case 2. Refer to the section on Interrupt (Section 6.6) for further details. Case [b] If Port 5 Input Status Change is used to wake up EM78P341N/342N/343N and the ICWE bit of the RE register is enabled before SLEP, WDT must be disabled. Hence, the EM78P341N/342N/343N can be awakened only with Case 3. Wake-up time is dependent on oscillator mode. In RC mode, Wake-up time is 32 clocks (for stable oscillators). In High Crystal mode, Wake-up time is 2ms and 32 clocks (for stable oscillators), and in low Crystal mode, Wake-up time is 500ms.
36 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM Case [c] If the Comparator output status change is used to wake-up the EM78P342N/ 343N and the CMPWE bit of the RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P342N/343N can be awakened only with Case 4. Wake-up time is dependent on oscillator mode. In RC mode the Wake-up time is 32 clocks (for stable oscillators). In High Crystal mode, Wake-up time is 2ms and 32 clocks (for stable oscillators), and in low Crystal mode, Wake-up time is 500ms. Case [d] If AD conversion completed is used to wake-up the EM78P341N/342N/343N and ADWE bit of RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P341N342N/343N can be awakened only with Case 5. The wake-up time is 15 TAD (ADC clock period). Case[e] If Low voltage detector is used to wake-up the EM78P341N/342N/343N and the LVDWE bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P341N/342N/343N can be awakened only with Case 6. Wake-up time is dependent on oscillator mode. If Port 5 Input Status Change Interrupt is used to wake up the EM78P341N/342N/343N (as in Case [b] above), the following instructions must be executed before SLEP: BC R3, 7 MOV A, @00xx1110b IOW IOCE0 WDTC MOV R5, R5 ENI (or DISI) MOV A, @xxxxxx1xb MOV RE MOV A, @xxxxxx1xb IOW IOCF0 SLEP ; Select Segment 0 ; Select WDT prescaler and Disable WDT ; ; ; ; Clear WDT and prescaler Read Port 5 Enable (or disable) global interrupt Enable Port 5 input change wake-up bit
; Enable Port 5 input change interrupt ; Sleep
Similarly, if the Comparator Interrupt is used to wake up the EM78P341N/342N/343N (as in Case [c] above), the following instructions must be executed before SLEP: BC MOV IOW MOV R3, 7 A, @xxx10XXXb IOC80 A, @00x11110b ; Select Segment 0 ; Select a comparator and P64 functions as CO pin ; Select WDT prescaler and Disable WDT, and enable comparator output status change interrupt ; Clear WDT and prescaler ; Enable (or disable) global interrupt ; Enable comparator output status change wake-up bit ; Sleep
IOW IOCE0 WDTC ENI (or DISI) MOV A, @xxx0x1xxb MOV SLEP RE
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 37
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM 6.5.1.1 Wake-up and Interrupt Modes Operation Summary The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows.
Wakeup Signal External interrupt Sleep Mode Idle Mode Green Mode Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Normal Mode Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction
Wake-up + interrupt x (if interrupt is enabled) + next instruction If enable ICWE bit If enable ICWE bit Wake-up Port 5 pin Wake-up + interrupt + interrupt change (if interrupt is enabled) (if interrupt is enabled) + next instruction + next instruction Wake-up + interrupt TCC overflow x (if interrupt is enabled) interrupt + next instruction If enable ADWE bit If enable ADWE bit AD Wake-up + interrupt Wake-up + interrupt conversion (if interrupt is enabled) (if interrupt enable) complete + next instruction + next instruction interrupt Fs and Fm don't stop Fs and Fm don't stop If enable CMPWE bit If enable CMPWE bit Wake-up Comparator Wake-up + interrupt + interrupt interrupt (if interrupt enable) (if interrupt enable) + next instruction + next instruction Wake-up High-pulse + interrupt width timer x (if interrupt enable) underflow + next instruction interrupt Wake-up Low-pulse + interrupt width timer x (if interrupt enable) underflow + next instruction interrupt Wake-up TCCA + interrupt overflow x (if interrupt enable) interrupt + next instruction Wake-up TCCB + interrupt overflow x (if interrupt enable) interrupt + next instruction Wake-up TCCC + interrupt overflow x (if interrupt enable) interrupt + next instruction If Enable LVDWE bit If Enable LVDWE bit Low Voltage Wake-up Wake-up + interrupt + interrupt Detector (if interrupt enable) (if interrupt enable) interrupt + next instruction + next instruction WDT Time out Low Voltage Reset RESET RESET RESET RESET
Interrupt x (if interrupt is enabled) Fs and Fm don't stop or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction RESET RESET Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction Interrupt (if interrupt enable) or next instruction RESET RESET
After wake up: 1. If interrupt is enabled interrupt+ next instruction 2. If interrupt is disabled next instruction 38 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
Idle Mode
DISI+IOCF0(EXIE) Bit 2 =1
Normal Mode
DISI + IOCF0 (EXIE) Bit 2=1 Next Instruction + Set RF (EXIF)=1 ENI + IOCF0 (EXIE) Bit 2=1 Interrupt Vector (003H) + Set RF (EXIF)=1 IOCF0 (ICIE) Bit 1=0
Green Mode
DISI + IOCF0 (EXIE) Bit 2=1 Next Instruction + Set RF (EXIF)=1 ENI + IOCF0 (EXIE) Bit 2=1 Interrupt Vector (003H) + Set RF (EXIF)=1 IOCF0 (ICIE) Bit 1=0
INT Pin
NA
Wake-up + next instruction Set RF (EXIF)=1 ENI + IOCF0(EXIE) Bit 2 =1 Wake-up + Interrupt Vector (003H) + Set RF (EXIF)=1
RE (ICWE) Bit 1=0, IOCF0 (ICIE) bit 1=0 Oscillator, TCC, TCCX and IR/PWM are stopped. Port 5 input status changed wake-up is invalid. RE (ICWE) Bit 1=0, IOCF0 (ICIE) Bit 1=1 Set RF (ICIF)=1, Oscillator, TCC, TCCX and IR/PWM are stopped. Port 5 input status changed wake-up is invalid. RE (ICWE) Bit 1=1, IOCF0 (ICIE) Bit 1=0 Port 5 Input Wake-up + Next Status Change Instruction Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ICWE) Bit1=1, DISI + IOCF0 (ICIE) Bit 1=1 Wake-up + Next Instruction + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ICWE) Bit 1=1, ENI + IOCF0 (ICIE) Bit 1=1 Wake-up + Interrupt Vector (006H) + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM are stopped.
RE (ICWE) Bit 1=0, IOCF0 (ICIE) Bit 1=0 Oscillator, TCC, TCCX and IR/PWM keep on running. Port5 input status changed wake-up is invalid. RE (ICWE) Bit 1=0, IOCF0 (ICIE) Bit 1=1 Set RF (ICIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Port5 input status changed wake-up is invalid. RE (ICWE) Bit 1=1, IOCF0 (ICIE) Bit1=0 Wake-up + Next Instruction Oscillator, TCC, TCCX and IR/PWM keep on running. RE (ICWE) Bit 1=1, DISI + IOCF0 (ICIE) Bit 1=1 Wake-up + Next Instruction + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM keep on running. RE (ICWE) Bit 1=1, ENI + IOCF0 (ICIE) Bit 1=1 Wake-up + Interrupt Vector (006H) + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM keep on running. DISI+IOCF0(TCIE) Bit 0 =1 Wake-up + next instruction Set RF (TCIF)=1 ENI + IOCF0(TCIE) Bit 0 =1 Wake-up + Interrupt Vector (009H) + Set RF (TCIF)=1
Port 5 input status change Port 5 input status change interrupted is invalid interrupted is invalid
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DISI + IOCF0 (ICIE) Bit 1=1
DISI + IOCF0 (ICIE) Bit 1=1
Next Instruction + Set RF (ICIF)=1
Next Instruction + Set RF (ICIF)=1
ENI + IOCF0 (ICIE) Bit 1=1
ENI + IOCF0 (ICIE) Bit 1=1
Interrupt Vector(006H) + Set RF (ICIF)=1
Interrupt Vector(006H) + Set RF (ICIF)=1
DISI + IOCF0 (TCIE) Bit 0=1 Next Instruction + Set RF (TCIF)=1 ENI + IOCF0 (TCIE) Bit 0=1 Interrupt Vector (009H) + Set RF (TCIF)=1
DISI + IOCF0 (TCIE) Bit 0=1 Next Instruction + Set RF (TCIF)=1 ENI + IOCF0 (TCIE) Bit 0=1 Interrupt Vector (009H) + Set RF (TCIF)=1
TCC Over Flow
NA
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 39
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=0 Clear R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=1 Set RF (ADIF)=1, R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ADWE) Bit 3=1, IOCE0 (ADIE) Bit 5=0 Wake-up + Next Instruction,
Idle Mode
RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=0 Clear R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running. RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=1 Set RF (ADIF)=1, R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running. RE (ADWE) Bit 3=1, IOCE0 (ADIE) Bit 5=0 Wake-up + Next Instruction, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed.
Normal Mode
IOCE0 (ADIE) Bit 5=0
Green Mode
IOCE0 (ADIE) Bit 5=0
AD conversion interrupted AD conversion interrupted is invalid is invalid
N/A
N/A
N/A
N/A
N/A
N/A
Oscillator, TCC, TCCX AD Conversion and IR/PWM keep on running. Wake-up when ADC completed. RE (ADWE) Bit 3=1, DISI + IOCE0 (ADIE) Bit 5=1 Wake-up + Next Instruction + RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed.
N/A
N/A
RE (ADWE) Bit 3=1, DISI + IOCE0 (ADIE) Bit 5=1
DISI + IOCE0 (ADIE) Bit 5=1
DISI + IOCE0 (ADIE) Bit 5=1
Wake-up + Next Instruction + RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. ENI + IOCE0 (ADIE) Bit 5=1 ENI + IOCE0 (ADIE) Bit 5=1 Next Instruction + RE (ADIF)=1 Next Instruction + RE (ADIF)=1
RE (ADWE) Bit 3=1, ENI RE (ADWE) Bit 3=1, ENI + + IOCE0 (ADIE) Bit 5=1 IOCE0 (ADIE) Bit 5=1 Wake-up + Interrupt Vector (00CH)+ RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. Wake-up + Interrupt Vector (00CH)+ RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed.
Interrupt Vector (00CH) + Set RE (ADIF)=1
Interrupt Vector (00CH) + Set RE (ADIF)=1
40 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
RE (CMPWE) Bit 2=0, IOCE0 (CMPIE) Bit 4=0 Comparator output status changed wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (CMPWE) Bit 2=0, IOCE0 (CMPIE) Bit 4=1 Set RE (CMPIF)=1, Comparator output status changed wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (CMPWE) Bit 2=1, IOCE0 (CMPIE) Bit 4=0 Wake-up + Next Instruction, Oscillator, TCC, TCCX and IR/PWM are stopped. RE (CMPWE) Bit 2=1, DISI + IOCE0 (CMPIE) Bit 4=1 Wake-up + Next Instruction + Set RE (CMPIF)=1, Oscillator, TCC, TCCX and IR/PWM are stopped. RE (CMPWE) Bit 2=1, ENI + IOCE0 (CMPIE) Bit 4=1 Wake-up + Interrupt Vector (00FH) + Set RE (CMPIF)=1,Oscillator, TCC, TCCX and IR/PWM are stopped.
Idle Mode
RE (CMPWE) Bit 2=0, IOCE0 (CMPIE) Bit 4=0 Comparator output status changed wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running. RE (CMPWE) Bit 2=0, IOCE0 (CMPIE) Bit 4=1 Set RE (CMPIF)=1, Comparator output status changed wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running. RE (CMPWE) Bit 2=1, IOCE0 (CMPIE) Bit 4=0 Wake-up + Next Instruction, Oscillator, TCC, TCCX and IR/PWM keep on running.
Normal Mode
IOCE0 (CMPIE) Bit 4=0
Green Mode
IOCE0 (CMPIE) Bit 4=0
Comparator output status Comparator output status change interrupt is invalid. change interrupt is invalid.
N/A
N/A
N/A
N/A
N/A
N/A
Comparator (Comparator Output Status Change)
N/A
N/A
RE (CMPWE) Bit 2=1, DISI + DISI + IOCE0 (CMPIE) IOCE0 (CMPIE) Bit 4=1 Bit 4=1
DISI + IOCE0 (CMPIE) Bit 4=1
Wake-up + Next Instruction + Set RE (CMPIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running.
Next Instruction + Set RE (CMPIF)=1
Next Instruction + Set RE (CMPIF)=1
RE (CMPWE) Bit 2=1, ENI + ENI + IOCE0 (CMPIE) IOCE0 (CMPIE) Bit 4=1 Bit 4=1 Wake-up + Interrupt Vector (00FH) + Set RE Interrupt Vector (00FH) (CMPIF)=1,Oscillator, TCC, + Set RE (CMPIF)=1 TCCX and IR/PWM keep on running. DISI + IOCF0 (HPWTIE) Bit 6=1 Wake-up +Next Instruction + Set RF (HPWTIF)=1 DISI + IOCF0 (HPWTIE) Bit 6=1 Next Instruction + Set RF (HPWTIF)=1 ENI + IOCF0 (HPWTIE) Bit 6 =1 Interrupt Vector (012H) + Set RF (HPWTIF)=1
ENI + IOCE0 (CMPIE) Bit 4=1
Interrupt Vector (00FH) + Set RE (CMPIF)=1
IR/PWM underflow interrupt (High-pulse width timer underflow interrupt) N/A
DISI + IOCF0 (HPWTIE) Bit 6=1 Next Instruction + Set RF (HPWTIF)=1 ENI + IOCF0 (HPWTIE) Bit 6 =1 Interrupt Vector (012H) + Set RF (HPWTIF)=1
ENI + IOCF0 (HPWTIE) Bit 6 =1 Wake-up +Interrupt Vector (012H) + Set RF (HPWTIF)=1
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 41
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
IR/PWM underflow interrupt (Low-pulse width timer underflow interrupt)
Sleep Mode
Idle Mode
DISI + IOCF0 (LPWTIE) Bit 7=1 Wake-up +Next Instruction + Set RF (LPWTIF)=1
Normal Mode
DISI + IOCF0 (LPWTIE) Bit 7=1 Next Instruction + Set RF (LPWTIF)=1 ENI + IOCF0 (LPWTIE) Bit 7 =1 Interrupt Vector (015H) + Set RF (LPWTIF)=1 DISI + IOCF0 (TCCAIE) Bit 3=1 Next Instruction + Set RF (TCCAIF)=1 ENI + IOCF0 (TCCAIE) Bit 3=1 Interrupt Vector (018H) + Set RF (TCCAIF)=1 DISI + IOCF0 (TCCBIE) Bit 4=1 Next Instruction + Set RF (TCCBIF)=1 ENI + IOCF0 (TCCBIE) Bit 4=1 Interrupt Vector (01BH) + Set RF (TCCBIF)=1 DISI + IOCF0 (TCCCIE) Bit 5=1 Next Instruction + Set RF (TCCCIF)=1 ENI + IOCF0 (TCCCIE) Bit 5=1 Interrupt Vector (01EH) + Set RF (TCCCIF)=1
Green Mode
DISI + IOCF0 (LPWTIE) Bit 7=1 Next Instruction + Set RF (LPWTIF)=1 ENI + IOCF0 (LPWTIE) Bit 7 =1 Interrupt Vector (015H) + Set RF (LPWTIF)=1 DISI + IOCF0 (TCCAIE) Bit 3=1 Next Instruction + Set RF (TCCAIF)=1 ENI + IOCF0 (TCCAIE) Bit 3=1 Interrupt Vector (018H) + Set RF (TCCAIF)=1 DISI + IOCF0 (TCCBIE) Bit 4=1 Next Instruction + Set RF (TCCBIF)=1 ENI + IOCF0 (TCCBIE) Bit 4=1 Interrupt Vector (01BH) + Set RF (TCCBIF)=1 DISI + IOCF0 (TCCCIE) Bit 5=1 Next Instruction + Set RF (TCCCIF)=1 ENI + IOCF0 (TCCCIE) Bit 5=1 Interrupt Vector (01EH) + Set RF (TCCCIF)=1
N/A
ENI + IOCF0 (LPWTIE) Bit 7 =1 Wake-up +Interrupt Vector (015H) + Set RF (LPWTIF)=1 DISI + IOCF0 (TCCAIE) Bit 3=1 Wake-up +Next Instruction + Set RF (TCCAIF)=1
TCCA Over Flow
N/A
ENI + IOCF0 (TCCAIE) Bit 3=1 Wake-up +Interrupt Vector (018H) + Set RF (TCCAIF)=1 DISI + IOCF0 (TCCBIE) Bit 4=1 Wake-up +Next Instruction + Set RF (TCCBIF)=1
TCCB Over Flow
N/A
ENI + IOCF0 (TCCBIE) Bit 4=1 Wake-up +Interrupt Vector (01BH) + Set RF (TCCBIF)=1 DISI + IOCF0 (TCCCIE) Bit 5=1 Wake-up +Next Instruction + Set RF (TCCCIF)=1
TCCC Over Flow
N/A
ENI + IOCF0 (TCCCIE) Bit 5=1 Wake-up +Interrupt Vector (01EH) + Set RF (TCCCIF)=1
42 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
RE (LVDWE) Bit 0=0, IOCD1 (LVDIE) Bit 3=0 Low voltage detector wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (LVDWE) Bit 0=0, IOCD1 (LVDIE) Bit 3=1 Set RE (LVDIF)=1, Low voltage detector wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (LVDWE) Bit 0=1, IOCD1 (LVDIE) Bit 3=0
Idle Mode
Normal Mode
Green Mode
IOCD1 (LVDIE) Bit 3=0
RE (LVDWE) Bit 0=0, IOCD1 IOCD1 (LVDIE) Bit 3=0 (LVDIE) Bit 3=0 Low voltage detector wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running.
Low voltage detector interrupted is invalid.
Low voltage detector interrupted is invalid.
RE (LVDWE) Bit 0=0, IOCD1 N/A (LVDIE) Bit 3=1 Set RE (LVDIF)=1, Low voltage detector wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running. N/A
N/A
N/A
RE (LVDWE) Bit 0=1, IOCD1 N/A (LVDIE) Bit 3=0 Wake-up + Next Instruction, Oscillator, TCC, TCCX and IR/PWM keep on running. N/A
N/A
Low Voltage Detector interrupt
Wake-up + Next Instruction, Oscillator, TCC, TCCX and IR/PWM are stopped. RE (LVDWE) Bit =1, DISI + IOCD1 (LVDIE) Bit 3=1 Wake-up + Next Instruction + Set RE (LVDIF)=1, Oscillator, TCC, TCCX and IR/PWM are stopped. RE (LVDWE) Bit 2=1, ENI + IOCD1 (LVDIE) Bit 3=1 Wake-up + Interrupt Vector (021H) + Set RE (LVDIF)=1,Oscillator, TCC, TCCX and IR/PWM are stopped.
N/A
RE (LVDWE) Bit 0=1, DISI + DISI + IOCD1 (LVDIE) IOCD1 (LVDIE) Bit 3=1 Bit 3=1
DISI + IOCD1 (LVDIE) Bit 3=1
Wake-up + Next Instruction + Set RE (LVDIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running.
Next Instruction + Set RE (LVDIF)=1
Next Instruction + Set RE (LVDIF)=1
RE (LVDWE) Bit0=1, ENI + IOCD1 (LVDIE) Bit 3=1
ENI + IOCD1 (LVDIE) Bit 3=1
ENI + IOCD1 (LVDIE) Bit 3=1
Wake-up + Interrupt Vector (021H) + Set RE Interrupt Vector (021H) (LVDIF)=1,Oscillator, TCC, + Set RE (LVDIF)=1 TCCX and IR/PWM keep on running. Wake-up + Reset (Address 0x00) Wake-up + Reset (Address 0x00) Reset (Address 0x00)
Interrupt Vector (021H) + Set RE (LVDIF)=1
WDT Time Out IOCE (WDTE) Bit 7=1 Low voltage reset
Wake-up + Reset (Address 0x00) Wake-up + Reset (Address 0x00)
Reset (Address 0x00)
Reset (Address 0x00)
Reset (Address 0x00)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 43
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.5.1.2 Register Initial Values after Reset The following summarizes the registers initialized values.
Address Name Reset Type
Bit Name Type N/A IOC50 Power-on /RESET and WDT Wake-up from Pin Change Bit Name Type N/A IOC60 Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on N/A IOC70 /RESET and WDT Wake-up from Pin Change Bit Name Power-on N/A IOC80 /RESET and WDT Wake-up from Pin Change Bit Name Power-on N/A IOC90 /RESET and WDT Wake-up from Pin Change Bit Name N/A IOCA0 (IR CR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name N/A IOCB0 (PDCR) Power-on /RESET and WDT Wake-up from Pin Change
Bit 7
C57
108C
Bit 6
C56
108C
Bit 5
C55 - 1 1 P C65
Bit 4
C54
341N
Bit 3
C53
341N
Bit 2
C52
341N
Bit 1
C51 - 1 1 P C61
341N
Bit 0
C50 - 1 1 P C60
341N
341N 343N 341N 343N 342N 342N
108C 342N 108C 342N 108C 342N 343N 343N 343N
0 0 0
1 1 P
0 0 0
1 1 P
0 0 0
1 1 P
0 0 0
1 1 P
0 0 0
1 1 P
C67 - 1 1 P X 0 0 P X 0 0 P
C66
108C 341N 342N
C64
C63
C62
343 108C 342N 108C 342N 108C 342N 108C 342N N 341N 343N 341N 343N 341N 343N 341N 343N
108C 342N 108C 342N 343N
343N
0 0 0 X 0 0 P X 0 0 P
1 1 P
0 0 0 X 0 0 P
1 1 P
0 0 0 X 0 0 P
1 1 P
0 0 0 X 0 0 P
1 1 P
0 0 0 X 0 0 P
1 1 P
0 0 0
1 1 P
0 0 0
1 1 P
C71 1 1 P
C70 1 1 P
CMPOUT 0 0 P
COS1 0 0 P
COS0 0 0 P X 0 0 P IRE 0 0 P /PD53 1 1 P
TCCAEN TCCATS TCCATE 0 0 P 0 0 P 0 0 P
TCCBHE TCCBEN TCCBTS TCCBTE 0 0 P 0 0 P 0 0 P 0 0 P
TCCCEN TCCCTS TCCCTE 0 0 P HF 0 0 P /PD52 1 1 P 0 0 P LGP 0 0 P /PD51 1 1 P 0 0 P IROUTE 0 0 P /PD50 1 1 P
TCCCSE TCCCS2 TCCCS1 TCCCS0 0 0 P /PD57 1 1 P 0 0 P /PD56 1 1 P 0 0 P /PD55 1 1 P 0 0 P /PD54 1 1 P
44 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on
Bit 7
/OD67 1 1 P /PH57 1 1 P WDTC 0 0 P
Bit 6
/OD66 1 1 P /PH56 1 1 P EIS 0 0 P
Bit 5
/OD65 1 1 P /PH55 1 1 P ADIE 0 0 P
Bit 4
/OD64 1 1 P /PH54 1 1 P CMPIE 0 0 P
Bit 3
/OD63 1 1 P /PH53 1 1 P PSWE 0 0 P
Bit 2
/OD62 1 1 P /PH52 1 1 P PSW2 0 0 P EXIE 0 0 P TCCA2 0 0 P TCCB2 0 0 P
Bit 1
/OD61 1 1 P /PH51 1 1 P PSW1 0 0 P ICIE 0 0 P TCCA1 0 0 P TCCB1 0 0 P
Bit 0
/OD60 1 1 P /PH50 1 1 P PSW0 0 0 P TCIE 0 0 P TCCA0 0 0 P TCCB0 0 0 P TCCBH 0 0 0 P TCCC0 0 0 P LTR0 0 0 P
N/A
IOCC0 (ODCR)
N/A
IOCD0 (PHCR1)
N/A
IOCE0
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
LPWTIE HPWTIE TCCCIE TCCBIE TCCAIE 0 0 P TCCA7 0 0 P TCCB7 0 0 P 0 0 P TCCA6 0 0 P TCCB6 0 0 P 0 0 P TCCA5 0 0 P TCCB5 0 0 P 0 0 P TCCA4 0 0 P TCCB4 0 0 P 0 0 P TCCA3 0 0 P TCCB3 0 0 P
N/A
IOCF0
/RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name
N/A
IOC51 (TCCA)
N/A
IOC61 (TCCB)
TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 0 0 P TCCC7 0 0 P LTR7 0 0 P 0 0 P TCCC6 0 0 P LTR6 0 0 P 0 0 P TCCC5 0 0 P LTR5 0 0 P 0 0 P TCCC4 0 0 P LTR4 0 0 P 0 0 P TCCC3 0 0 P LTR3 0 0 P 0 0 P TCCC2 0 0 P LTR2 0 0 P 0 0 P TCCC1 0 0 P LTR1 0 0 P
N/A
IOC71 (TCCBH)
Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-p from Pin Change
N/A
IOC81 (TCCC)
N/A
IOC91 (LTR)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 45
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name
Bit 7
HTR7 0 0 P HTSE 0 0 P
Bit 6
HTR6 0 0 P HTS2 0 0 P
Bit 5
HTR5 0 0 P HTS1 0 0 P
Bit 4
HTR4 0 0 P HTS0 0 0 P
Bit 3
HTR3 0 0 P LTSE 0 0 P
Bit 2
HTR2 0 0 P LTS2 0 0 P
Bit 1
HTR1 0 0 P LTS1 0 0 P
Bit 0
HTR0 0 0 P LTS0 0 0 P TCCPC 0 0 0 P LVD0 1 1 P HS0 0 0 P /PH60 1 1 P PST0 0 0 P - U P P - 0 0 P
N/A
IOCA1 (HTR)
N/A
IOCB1 (HLTS)
TCCPC7 TCCPC6 TCCPC5 TCCPC4 TCCPC3 TCCPC2 TCCPC1 0 0 P TYPE1 1 P P WDPTS 1 P P /PH67 1 1 P INTE 1 1 P - U P P - 0 0 P 0 0 P TYPE0 1 P P TIMERS C 1 1 P /PH66 1 1 P INT 0 0 P - U P P - 0 0 P 0 0 P LVR1 1 P P CPUS 1 1 P /PH65 1 1 P TS 1 1 P - U P P - 0 0 P 0 0 P LVR0 1 P P IDLE 1 1 P /PH64 1 1 P TE 1 1 P - U P P - 0 0 P 0 0 P LVDIE 0 0 P HS3 0 0 P /PH63 1 1 P PSTE 0 0 P - U P P - 0 0 P 0 0 P LVDEN 0 P P HS2 0 0 P /PH62 1 1 P PST2 0 0 P - U P P - 0 0 P 0 0 P LVD1 1 1 P HS1 0 0 P /PH61 1 1 P PST1 0 0 P - U P P - 0 00 P
N/A
IOCC1 (TCCPC)
Power-on /RESET and WDT Wake-up from Pin Change Bit Name
N/A
Power-on IOCD1 (LVD CR) /RESET and WDT (ROMLESS) Wake-up from Pin Change HS1
N/A
IOCE1 Power-on (HSC) (ROMLESS) /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on
N/A
IOCF1 (PHCR2)
N/A
CONT
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x00
R0(IAR)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x01
R1(TCC)
/RESET and WDT Wake-up from Pin Change
46 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on
Bit 7
- 0 0
Bit 6
- 0 0
Bit 5
- 0 0
Bit 4
- 0 0
Bit 3
- 0 0
Bit 2
- 0 0
Bit 1
- 0 0
Bit 0
- 0 0
0x02
R2 (PC)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
Jump to address 0x06 or continue to execute next instruction RST 0 0 P X 0 0 0 P57 1 1 P P67 1 1 P - 0 0 P - 0 0 0 VREFS 0 0 P CALI 0 0 P IOCS 0 0 P BS 0 0 P P56 1 1 P P66 1 1 P - 0 0 P - 0 0 0 CKR1 0 0 P SIGN 0 0 P PS0 0 0 P X U P P P55 1 1 P P65 1 1 P - 0 0 P - 0 0 0 CKR0 0 0 P VOF[2] 0 0 P T 1 T T X U P P P54 1 1 P P64 1 1 P - 0 0 P - 0 0 0 ADRUN 0 0 P VOF[1] 0 0 P P 1 t t X U P P P53 1 1 P P63 1 1 P - 0 0 P ADE3 0 0 P ADPD 0 0 P VOF[0] 0 0 P Z U P P X U P P P52 1 1 P P62 1 1 P - 0 0 P ADE2 0 0 P - 0 0 0 - 0 0 P DC U P P X U P P P51 1 1 P P61 1 1 P P71 1 1 P ADE1 0 0 P ADIS1 0 0 P - 0 0 P C U P P X U P P P50 1 1 P P60 1 1 P P70 1 1 P ADE0 0 0 P ADIS0 0 0 P - 0 0 P
0x03
R3 (SR)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x04
R4 (RSR)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x05
R5
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x06
R6
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x7
R7
/RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change
0x8
R8 (AISR)
0x9
R9 (ADCON)
0xA
RA (ADOC)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 47
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name
Bit 7
AD11 U U P "0" 0 0 0 AD7 U U P -0 0 P
Bit 6
AD10 U U P "0" 0 0 0 AD6 U U P - 0 0 P
Bit 5
AD9 U U P "0" 0 0 0 AD5 U U P ADIF 0 0 P
Bit 4
AD8 U U P "0" 0 0 0 AD4 U U P CMPIF 0 0 P
Bit 3
AD7 U U P AD11 U U P AD3 U U P ADWE 0 0 P
Bit 2
AD6 U U P AD10 U U P AD2 U U P CMPWE 0 0 P EXIF 0 0 P - U P P
Bit 1
AD5 U U P AD9 U U P AD1 U U P ICWE 0 0 P ICIF 0 0 P - U P P
Bit 0
AD4 U U P AD8 U U P AD0 U U P - 0 0 P TCIF 0 0 P - U P P
0XB
RB (ADDATA)
0XC
Power-on RC (ADDATA1H) /RESET and WDT Wake-up from Pin Change Bit Name Power-on
0XD
RD (ADDATA1L0) /RESET and WDT Wake-up from Pin Change Bit Name
0xE
RE (ISR2)
Power-on /RESET and WDT Wake-up from Pin Change Bit Name
LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P
0xF
RF (ISR1)
Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x10~0x3F
R10~R3F
/RESET and WDT Wake-up from Pin Change
Legend: "-" = not used "u" = unknown or don't care
"P" = previous value before reset "t" = check "Reset Type" Table in Section 6.5.2
48 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.5.1.3 Controller Reset Block Diagram
VDD D Oscillator CLK CLR Power-on Reset Voltage Detector Q CLK
ENWDTB WDT Timeout WDT Setup time Reset
/RESET
Fig. 6-8 Controller Reset Block Diagram
6.5.2 The T and P Status under Status (R3) Register
A reset condition is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) The values of RST, T, and P as listed in the table below, are used to check how the processor wakes up.
Reset Type Power-on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-up on pin change during SLEEP mode *P: Previous status before reset RST 0 0 0 0 0 1 T 1 *P 1 0 0 1 P 1 *P 0 1 0 0
The following shows the events that may affect the status of T and P. Event
Power-on WDTC instruction WDT time-out SLEP instruction Wake-up on pin changed during SLEEP mode *P: Previous value before reset
RST
0 *P 0 *P 1
T
1 1 0 1 1
P
1 1 *P 0 0
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.6 Interrupt
The EM78P341N/342N/343N has six interrupts as listed below: 1. TCC, TCCA, TCCB, TCCC overflow interrupt 2. Port 5 Input Status Change Interrupt 3. External interrupt [(P60, /INT) pin] 4. Analog to Digital conversion completed 5. IR/PWM underflow interrupt 6. When the comparators status changes (not applicable to EM78P341N) 7. Low voltage detector interrupt Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV R5,R5") is necessary. Each Port 5 pin will have this feature if its status changes. The Port 5 Input Status Change Interrupt will wake up the EM78P341N/342N/343N from sleep mode if it is enabled prior to going into sleep mode by executing SLEP instruction. When wake up occurs, the controller will continue to execute program in-line if the global interrupt is disabled. If enabled, the global interrupt will branch out to the interrupt vector 006H. External interrupt equipped with digital noise rejection circuit (input pulse less than system clock time) is eliminated as noise. However, under Low Crystal oscillator (LXT) mode the noise rejection circuit will be disabled. Edge selection is possible with INTE of CONT. When an interrupt is generated by the External interrupt (when enabled), the next instruction will be fetched from address 003H. Refer to the Word 1 Bits 9 & 8 (Section 6.14.2, Code Option Register (Word 1)) for digital noise rejection definition. RF and RE are the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flag (except for the ICIF bit) in the Interrupt Status Register (RF) is set regardless of the ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0 (refer to figure below). The RETI instruction ends the interrupt routine and enables the global interrupt (the ENI execution). When an interrupt is generated by the Timer clock/counter (when enabled), the next instruction will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB, and TCCC respectively). When an interrupt generated by the AD conversion is completed (when enabled), the next instruction will be fetched from Address 00CH.
50 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
When an interrupt is generated by the High time / Low time down counter underflow (when enabled), the next instruction will be fetched from Addresses 012 and 015H (High time and Low time respectively). When an interrupt is generated by the Comparators (when enabled), the next instruction will be fetched from Address 00FH (Comparator interrupt). When an interrupt is generated by the Low Voltage Detect (when enabled), the next instruction will be fetched from Address 021 (Low Voltage Detector interrupt). Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4 registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and R4 will be replaced by the new interrupt. After an interrupt service routine is completed, the ACC, R3, and R4 registers are restored.
VCC
D /IRQn
P R C L
Q _ Q RFRD
IRQn INT IRQm ENI/DISI
CLK RF
Q _ Q
P R C L
D CLK IOCFWR
IOD
IOCF /RESET
IOCFRD
RFWR
Fig. 6.9 Interrupt Input Circuit
Interrupt Sources ACC ENI/DISI R3 R4
Interrupt occurs Stack ACC Sack R3 Stack R4
RETI
Fig. 6.10 Interrupt Backup Diagram
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
In EM78P341N/342N/343N, each individual interrupt source has its own interrupt vector as depicted in the table below.
Interrupt Vector 003H 006H 009H 00CH 00FH 012H 015H 018H 01BH 01EH 021H Interrupt Status External interrupt Port 5 pin change TCC overflow interrupt AD conversion complete interrupt Comparator interrupt High-pulse width timer underflow interrupt Low-pulse width timer underflow interrupt TCCA overflow interrupt TCCB overflow interrupt TCCC overflow interrupt Low Voltage Detector interrupt Priority* 2 3 4 5 6 7 8 9 10 11 1
*Priority: 1 = highest ; 11 = lowest priority
NOTE Comparator interrupt is not applicable to EM78P341N.
52 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.7 Analog-To-Digital Converter (ADC)
The analog-to-digital circuitry consist of a 4-bit analog multiplexer; three control registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA/RB, ADDATA1H/RC, & ADDATA1L/RD), and an ADC with 12-bit resolution as shown in the functional block diagram below. The analog reference voltage (Vref) and the analog ground are connected via separate input pins. The ADC module utilizes successive approximation to convert the unknown analog signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and ADDATA1L. Input channels are selected by the analog input multiplexer via the ADCON register Bits ADIS1 and ADIS0.
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Fsco 4-1 MUX Internal RC 7~0 AISR 1 ADCON 0 6 ADCON DATA BUS 5 RF 3 11 10 9 8 7 6 5 4 3 2 1 0 4 ADCON 3 Vref
ADC ( successive approximation )
Power-Down Start to Convert
ADDATA1H
ADDATA1L
Fig. 6-11 Analog-to-Digital Conversion Functional Block Diagram
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)
6.7.1.1 R8 (AISR: ADC Input Select Register)
Bit 7 ADE7 Bit 6 ADE6 Bit 5 ADE5 Bit 4 ADE4 Bit 3 ADE3 Bit 2 ADE2 Bit 1 ADE1 Bit 0 ADE0
AISR register defines the P5, P6, P7 pins as analog inputs or as digital I/O, individually. Bit 7 (ADE7): AD converter enable bit of P57 pin 0 = Disable ADC7, P57 functions as I/O pin 1 = Enable ADC7 to function as analog input pin Bit 6 (ADE6): AD converter enable bit of P55 pin 0 = Disable ADC6, P55 functions as I/O pin 1 = Enable ADC6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P70 pin 0 = Disable ADC5, P70 functions as I/O pin 1 = Enable ADC5 to function as analog input pin
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(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 4 (ADE4): AD converter enable bit of P67 pin 0 = Disable ADC4, P67 functions as I/O pin 1 = Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P53 pin 0 = Disable ADC3, P53 functions as I/O pin 1 = Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P52 pin 0 = Disable ADC2, P53 functions as I/O pin 1 = Enable ADC2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P51 pin 0 = Disable ADC1, P51 functions as I/O pin 1 = Enable ADC1 to function as analog input pin Bit 0 (ADE0): AD converter enable bit of P50 pin 0 = Disable ADC0, P50 functions as I/O pin 1 = Enable ADC0 to function as analog input pin 6.7.1.2 R9 (ADCON: AD Control Register)
Bit 7 VREFS Bit 6 CKR1 Bit 5 CKR0 Bit 4 ADRUN Bit 3 ADPD Bit 2 ADIS2 Bit 1 ADIS1 Bit 0 ADIS0
The ADCON register controls the operation of the AD conversion and decides which pin should be currently active. Bit 7(VREFS): The input source of the ADC Vref 0 = The ADC Vref is connected to Vdd (default value), and the VREF/TCC/P54 pin carries out the P54 function 1 = The ADC Vref is connected to VREF/TCC/P54
NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 (TS) must be "0". The P54/TCC/VREF pin priority is as follows: P54/TCC/VREF Pin Priority High VREF Medium TCC Low P54
54 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of ADC oscillator clock rate 00 = 1: 16 (default value) 01 = 1: 4 10 = 1: 64 11 = 1: 8
CPUS 1 1 1 1 0 CKR1: CKR0 00 01 10 11 xx Operation Mode Fosc/16 Fosc/4 Fosc/64 Fosc/8 Internal RC Max. Operation Frequency 4MHz 1MHz 16MHz 2MHz -
Bit 4 (ADRUN): ADC starts to RUN 1 = an AD conversion is started. This bit can be set by software. 0 = Reset upon completion of the conversion. This bit cannot be reset through software Bit 3 (ADPD): ADC Power-down mode. 1 = ADC is operating 0 = switch off the resistor reference to save power even while the CPU is operating. Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select 000 = ADIN0/P50 001 = ADIN1/P51 010 = ADIN2/P52 011 = ADIN3/P53 100 = ADIN0/P67 101 = ADIN1/P70 110 = ADIN2/P55 111 = ADIN3/P57 These bits can only be changed when the ADIF bit and the ADRUN bit are both LOW. 6.7.1.3 RA (ADOC: AD Offset Calibration Register)
Bit 7 CALI Bit 6 SIGN Bit 5 VOF[2] Bit 4 VOF[1] Bit 3 VOF[0] Bit 2 - Bit 1 - Bit 0 -
Bit 7 (CALI): Calibration enable bit for ADC offset 0 = disable Calibration 1 = enable Calibration Bit 6 (SIGN): Polarity bit of offset voltage 0 = Negative voltage 1 = Positive voltage
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(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2] 0 0 0 0 1 1 1 1 VOF[1] 0 0 1 1 0 0 1 1 VOF[0] 0 1 0 1 0 1 0 1 EM78P342N/343N 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB ICE342N 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
Bit 2 ~ Bit 0: Unimplemented, read as `0'.
6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
6.7.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of AD converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2s for each K of the analog source impedance and at least 2s for the low-impedance source. The maximum recommended impedance for analog source is 10K at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion is started.
6.7.4 AD Conversion Time
CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at a maximum frequency without sacrificing the AD conversion accuracy. For the EM78P342N/343N, the conversion time per bit is 4s. The table below shows the relationship between Tct and the maximum operating frequencies.
CKR1: CKR0 Operation Mode 00 01 10 11 Fsco/16 Fsco/4 Fsco/64 Fsco/8 Max. Operation Max. Conversion Max. Conversion Rate Frequency Rate/Bit 4 MHz 1MHz 16MHz 2MHz 250kHz (4s) 250kHz (4s) 250kHz( 4s) 250kHz (4s) 15x4s=60s(16.7kHz) 15x4s=60s(16.7kHz) 15x4s=60s(16.7kHz) 15x4s=1065s(16.7kHz)
NOTE
Pin not used as an analog input pin can be used as a regular input or output pin. During conversion, do not perform output instruction to maintain precision for all of the pins.
56 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.7.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD conversion remains operational during sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillator, TCC, TCCA, TCCB, TCCC and AD conversion. The AD Conversion is considered completed as determined by: 1. ADRUN bit of R9 register is cleared to "0". 2. ADIF bit of RE register is set to "1". 3. ADWE bit of the RE register is set to "1." Wake-up from ADC conversion (where it remains in operation during sleep mode). 4. Wake-up and executes the next instruction if ADIE bit of IOCE0 is enabled and the "DISI" instruction is executed. 5. Wake-up and enters into Interrupt vector (Address 0x00C) if ADIE bit of IOCE0 is enabled and the "ENI" instruction is executed. 6. Enters into Interrupt vector (Address 0x00C) if ADIE bit of IOCE0 is enabled and the "ENI" instruction is executed. The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise, the AD conversion will be shut off, no matter what the status of ADPD bit is.
6.7.6 Programming Process/Considerations
6.7.6.1 Programming Process Follow these steps to obtain data from the ADC: 1. Write to the seven bits (ADE7:ADE0) on the R8 (AISR) register to define the characteristics of R5 (digital I/O, analog channels, or voltage reference pin) 2. Write to the R9/ADCON register to configure the AD module: a) Select the ADC input channel (ADIS2: ADIS0) b) Define the AD conversion clock rate (CKR1: CKR0) c) Select the VREFS input source of the ADC d) Set the ADPD bit to 1 to begin sampling 3. Set the ADWE bit, if the wake-up function is employed 4. Set the ADIE bit, if the interrupt function is employed 5. Write "ENI" instruction, if the interrupt function is employed 6. Set the ADRUN bit to 1 7. Write "SLEP" instruction or Polling. 8. Wait for wake-up, ADRUN bit is cleared to "0", interrupt flag (ADIF) is set "1," or ADC interrupt occurs.
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EM78P341N/342N/343N
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9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the ADC input channel changes at this time, the ADDATA, ADDATA1H, and ADDATA1L values can be cleared to `0'. 10. Clear the interrupt flag bit (ADIF) 11. For the next conversion, go to Step 1 or Step 2 as required. At least two Tct is required before the next acquisition starts. NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on the I/O pins during AD conversion.
6.7.6.2 Sample Demo Programs A. Define a General Register R_0 == 0 PSW == 3 PORT5 == 5 PORT6 == 6 R_E== 0XE ; Indirect addressing register ; Status register
; Interrupt status register
B. Define a Control Register IOC50 == 0X5 IOC60 == 0X6 C_INT== 0XF ; Control Register of Port 5 ; Control Register of Port 6 ; Interrupt Control Register
C. ADC Control Register ADDATA == 0xB AISR == 0x08 ADCON == 0x9 ; The contents are the results of ADC ; ADC input select register ;7 6 5 4 3 2 1 0 ; VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
D. Define Bits in ADCON ADRUN == 0x4 ADPD == 0x3 E. Program Starts ORG 0 JMP INITIAL ; Initial address ; ; ADC is executed as the bit is set ; Power Mode of ADC
ORG 0x0C ; Interrupt vector JMP CLRRE ; ; ;(User program section) ; ;
58 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
CLRRE: MOV A,RE AND A, @0BXX0XXXXX ; To clear the ADIF bit, "X" by application MOV RE,A BS ADCON, ADRUN ; To start to execute the next AD conversion if necessary RETI INITIAL: MOV A,@0B00000001 ; To define P50 as an analog input MOV AISR,A MOV A,@0B00001000 ; To select P50 as an analog input channel, and AD power on MOV ADCON,A ; To define P50 as an input pin and set clock rate at fosc/16 En_ADC: MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others IOW PORT5 ; are dependent on applications MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, "X" by application MOV RE,A MOV A, @0BXXXX1XXX ; Enable the ADIE interrupt function of ADC, "X" by application IOW C_INT ENI ; Enable the interrupt function BS ADCON, ADRUN ; Start to run the ADC
; If the interrupt function is employed, the following three lines may be ignored ;If Sleep: SLEP ; ;(User program section) ; or ;If Polling: POLLING: JBC ADCON, ADRUN JMP POLLING
; To check the ADRUN bit continuously; ; ADRUN bit will be reset as the AD conversion is completed
; ;(User program section) ;
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.8 Infrared Remote Control Application/PWM Waveform Generation
6.8.1 Overview
This LSI can easily output infrared carrier or PWM standard waveform. As illustrated below, the IR and PWM waveform generation function include an 8-bit down count timer/counter, high-time, low-time, and IR control register. The IROUT pin waveform is determined by IOCA0 (IR and TCCC scale control register), IOCB1 (high-time rate, low-time rate control register), IOC81 (TCCC counter), IOCA1 (high-time register), and IOC91 (low-time register).
FT:CLK(Fosc)
8 Bit counter 8 Bit counter Scale (IOCA0) Scale (IOCB1) 8-to-1 MUX 8
8 Bit counter Scale (IOCB1)
8-to-1 MUX
8-to-1 MUX
Auto-reload buffer (High-time)(IOCA1)
8bit binary down counter 8
8bit binary down counter 8
8
Auto-reload buffer (Low-time)(IOC91)
Fcarrier
8bit binary down counter 8 Auto-reload buffer (TCCC)(IOC81)
H/W Modulator
HF
LG
IR
IROUT
Underflow Interrupt HPWTIF LPWTIF
Fig. 6-12 IR/PWM System Block Diagram
NOTE Details of the Fcarrier high time width and low time width are explained below: Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale(IOCA0) }
High time width = { [1+decimal high-time value (IOCA1)] * High time Scale(IOCB1) } / FT Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale(IOCB1) } / FT Where FT is the system clock FT=Fosc/1(CLK=2) FT=Fosc/2(CLK=4)
When an interrupt is generated by the High time down counter underflow (when enabled), the next instruction will be fetched from Address 018 and 01BH (High time and Low time respectively).
60 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.8.2 Function Description
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low-time segments of the pulse.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE IROUT
Fig. 6-13a LGP=0, HF=1, IROUT Pin Output Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is determined by the high time width and low time width instead. This mode can produce standard PWM waveform.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE IROUT
Fig. 6-13b LGP=0, HF=0, IROUT Pin Output Waveform
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low-time segments of the pulse. When IRE goes low from high, the output waveform of IROUT will keep transmitting until high-time interrupt occurs.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE IROUT
IR disable Always high-level
Fig. 6-13c LGP=0, HF=1, When IRE goes Low from High, IROUT Pin Outputs Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is determined by high time width and low time width. This mode can produce standard PWM waveform when IRE goes low from high. The output waveform of IROUT will keep on transmitting until high-time interrupt occurs.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start IRE IR disable Always high-level
IROUT
Fig. 6-13d LGP=0, HF=0, When IRE goes Low from High, Irout Pin Output Waveform
62 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=1 and HF=1. When this bit is set to high level, the high-time segment of the pulse is ignored. So, IROUT waveform output is determined by low-time width.
Fcarrier
low time width
low time width
low time width
HF
Start
IRE IROUT
Fig. 6-13e LGP=1 and HP=1, IROUT Pin Output Waveform
IR disable
Always high-level
6.8.3
Programming the Related Registers
When defining IR/PWM, refer to the operation of the related registers as shown in the tables below. IR/PWM Related Control Registers
Address 0x09 0X0A 0x0F 0X0B Name IOC90 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 IRE/0 Bit 2 Bit 1 Bit 0
TCCBHE/0TCCBEN/0 TCCBTS/0 TCCBTE/0
TCCCEN/0TCCCTS/0 TCCCTE/0 HF/0 EXIE/0 LTS2/0 LGP/0 ICIE/0 LTS1/0 IROUTE/0 TCIE/0 LTS0/0
IR CR TCCCSE/0 TCCCS2/0 TCCCS1/0 TCCCS0/0 /IOCA0 IMR /IOCF0 HLTS /IOCB1
LPWTIE/0 HPWTIE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0 HTSE/0 HTS2/0 HTS1/0 HTS0/0 LTSE/0
IR/PWM Related Status/Data Registers
Address 0x0F 0x06 0X09 0X0A Name ISR/RF TCCC /IOC81 LTR /IOC91 HTR /IOCA1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIF/0 Bit 1 ICIF/0 Bit 0 TCIF/0
LPWTIF/0 HPWTIF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0 LTR7/0 HTR7/0 LTR6/0 HTR6/0 LTR5/0 HTR5/0 LTR4/0 HTR4/0 LTR3/0 HTR3/0 LTR2/0 HTR2/0 LTR1/0 HTR1/0 LTR0/0 HTR0/0
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.9 Timer/Counter
6.9.1 Overview
Timer A (TCCA) is an 8-bit clock counter. Timer B (TCCB) is a 16-bit clock counter. Timer C (TCCC) is an 8-bit clock counter that can be extended to 16-bit clock counter with programmable scalers. TCCA, TCCB, and TCCC can be read and written to, and are cleared at every reset condition.
6.9.2 Function Description
Set predict value TCCAEN Set TCCAIF TCCA Overflow System clock or External input System clock or External input TCCB Overflow 8-to-1 MUX Set predict value TCCBEN Set TCCBIF TCCC Overflow TCCCS1 ~ TCCCS0 Set predict value TCCCEN Set TCCCIF
8 Bit counter System clock or External input
Fig. 6.14 TIMER Block Diagram
Each signal and block of the above Timer block diagram is described as follows:
TCCX: Timer A~C register. TCCX is incremented until it matches with zero, and then reloads the predicted value. When writing a value to TCCX, the predicted value and TCCX value become the set value. When reading from TCCX, the value will be the TCCX direct value. When TCCXEN is enabled, the reloading of the predicted value to TCCX, TCCXIE is also enabled. TCCXIF will be set at the same time. It is an up counter. TCCA Counter (IOC51):
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written to, and cleared on any reset condition and is an Up Counter.
NOTE TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1 (CLK=2)] TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2 (CLK=4)]
TCCB Counter (IOC61):
IOC61 is an 8-bit clock counter for the least significant byte of TCCBX (TCCB). It can be read, written, and cleared on any reset condition and is an Up Counter.
64 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
TCCBH / MSB Counter (IOC71):
IOC71 is an 8-bit clock counter for the most significant byte of TCCBX (TCCBH). It can be read, written to, and cleared on any reset condition. When TCCBHE (IOC90) is "0," then TCCBH is disabled. When TCCBHE is"1," then TCCB is a 16-bit length counter.
NOTE When TCCBH is Disabled: TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1 (CLK=2)] TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2 (CLK=4)] When TCCBH is Enabled: TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1 (CLK=2)} TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2 (CLK=4)}
TCCC Counter (IOC81):
IOC81 (TCCC) is an 8-bit clock counter. It can be read, written to, and cleared on any reset condition. If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). The TCCC value will then be the TCCC predicted value. When HP = 0 or IRE = 0. The TCCC is an Up Counter.
NOTE In TCCC Up Counter mode: TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1(CLK=2)] TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2(CLK=4)]
When HP = 1 and IRE = 1, the TCCC counter scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation.
NOTE In IR mode: Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] x TCCC Scale (IOCA0) } FT is system clock: FT = Fosc/1 (CLK=2) FT = Fosc/2 (CLK=4)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 65
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.9.3 Programming the Related Registers
When defining TCCX, refer to the operation of its related registers as shown in the tables below. TCCX Related Control Registers:
Address 0x08 0x09 0x0A 0x0F Name IOC80 IOC90 IR CR /IOCA0 IMR /IOCF0 Bit 7 0 Bit 6 0 Bit 5 CPOUT/0 Bit 4 COS1/0 TCCBTE /0 Bit 3 COS0/0 0 IRE/0 Bit 2 Bit 1 Bit 0 TCCATE /0
TCCAEN TCCATS /0 /0
TCCBHE TCCBEN TCCBTS /0 /0 /0
TCCCEN TCCCTS TCCCTE /0 /0 /0 HF/0 EXIE/0 LGP/0 ICIE/0 IROUTE/0 TCIE/0
TCCCSE TCCCS2 TCCCS1/ TCCCS0 /0 /0 0 /0
LPWTE/0 HPWTE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0
Related TCCX Status/Data Registers:
Address 0x0F 0x05 0x06 0x07 0x08 Name ISR/RF TCCA /IOC51 TCCB /IOC61 TCCBH /IOC71 TCCC /IOC81 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIF/0 Bit 1 ICIF/0 Bit 0 TCIF/0
LPWTF/0 HPWTF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
TCCA7/0 TCCA6/0 TCCA5/0 TCCA4/0 TCCA3/0 TCCA2/0 TCCA1/0 TCCA0/0 TCCB7/0 TCCB6/0 TCCB5/0 TCCB4/0 TCCB3/0 TCCB2/0 TCCB1/0 TCCB0/0 TCCBH7 /0 TCCBH6 /0 TCCBH5 /0 TCCBH4 /0 TCCBH3 /0 TCCBH2 /0 TCCBH1 /0 TCCBH0 /0
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0
6.10 Comparator
The EM78P342N/343N has one comparator which has two analog inputs and one output. The comparator can be employed to wake up the system from sleep mode. The Figure at right shows the comparator circuit.
Cin Cin+
Cin Cin+
CMP +
CO
Output
10mV
Fig. 6.15 Comparator Operating Mode
66 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.10.1 External Reference Signal
The analog signal that is presented at Cin - is compared to the signal at Cin+. The digital output (CO) of the comparator is adjusted accordingly by taking into consideration the following notes:
NOTE The reference signal must be between Vss and Vdd. The reference voltage can be applied to either pin of the comparator. Threshold detector applications may be of the same reference. The comparator can operate from the same or different reference sources.
6.10.2 Comparator Outputs
The compared result is stored in the CMPOUT of IOC80. The comparator outputs are sent to CO (P64) by programming Bit 4 & Bit 3 of the IOC80 register to <1,0>. See table under Section 6.2.4, IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits function description. The following figure shows the Comparator Output block diagram. To C0 From OP I/O CMRD
EN Q
EN D
Q To CMPOUT
D
RESET To CPIF CMRD From other comparator
Fig. 6-16 Comparator Output Configuration
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 67
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.10.3 Using a Comparator as an Operation Amplifier
The comparator can be used as an operation amplifier if a feedback resistor is externally connected from the input to the output. In this case, the Schmitt trigger can be disabled for power saving purposes, by setting Bit 4, Bit 3 of the IOC80 register to <1,1>. See table under Section 6.2.4, IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits function description.
NOTE Under Operation Amplifier: The CMPIE (IOCE0.4), CMPWE (RE.2), and CMPIF (RE.4) bits are invalid. The comparator interrupt is invalid. The comparator wake-up is invalid.
6.10.4 Comparator Interrupt
CMPIE (IOCE0.4) must be enabled for the "ENI" instruction to take effect Interrupt is triggered whenever a change occurs on the comparator output pin The actual change on the pin can be determined by reading the Bit CMPOUT, IOC80<5>. CMPIF (RE.4), the comparator interrupt flag, can only be cleared by software
6.10.5 Wake-up from Sleep Mode
If the CMPWE bit of the RE register is set to "1," the comparator remains active and the interrupt remains functional, even under SLEEP mode. If a mismatch occurs, the change will wake up the device from SLEEP mode. The power consumption should be taken into consideration for the benefit of energy conservation. If the function is unemployed during SLEEP mode, turn off the comparator before entering into sleep mode. The Comparator is considered completed as determined by:
1. COS1 and COS0 bits of IOC80 register setting selects Comparator. 2. CMPIF bit of RE register is set to "1". 3. CMPWE bit of RE register is set to "1". Wakes-up from Comparator (where it
remains in operation during sleep mode)
4. Wakes-up and executes the next instruction, if CMPIE bit of IOCE0 is enabled and
the "DISI" instruction is executed.
5. Wake-up and enters into Interrupt vector (address 0x00F), if ADIE bit of IOCE0 is
enabled and the "ENI" instruction is executed
6. Enters into Interrupt vector (address 0x00F), if CMPIE bit of IOCE0 is enabled and
the "ENI" instruction is executed.
68 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.11 Oscillator
6.11.1 Oscillator Modes
The EM78P341N/342N/343N can be operated in six different oscillator modes, such as High Crystal oscillator mode 1 (HXT1), High Crystal oscillator mode 2 (HXT2), Low Crystal oscillator mode 1 (LXT1), Low Crystal oscillator mode 2 (LXT2), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC). You can select one of them by programming the OSC2, OCS1, and OSC0 in the CODE Option register. The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
Oscillator Modes ERC (External RC oscillator mode); P70/OSCO acts as P70 ERC (External RC oscillator mode); P70/OSCO acts as OSCO IRC (Internal RC oscillator mode); P70/OSCO acts as P70 IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO 3 LXT1 (Frequency range of XT mode is 1MHz ~ 100kHz) 3 HXT1 (Frequency range of XT mode is 20MHz ~ 6MHz) 3 LXT2 (Frequency range of XT mode is 32kHz) 3 HXT2 (Frequency range of XT mode is 6MHz ~ 1MHz) (default)
1 2 3
OSC2 0 0 0 0 1 1 1 1
OSC1 0 0 1 1 0 0 1 1
OSC0 0 1 0 1 0 1 0 1
1 1
2 2
In ERC mode, OSCI is used as oscillator pin. OSCO/P50 is defined by code option Word 0 Bit 6 ~ Bit 4. In IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4. In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot and should not be defined as normal I/O pins.
The maximum operating frequency limit of crystal/resonator at different VDDs, are as follows:
Conditions VDD 1.7 Two clocks 3.0 4.0 Max. Freq. (MHz) 4 16 20
6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P341N/342N/343N can be driven by an external clock signal through the OSCI pin as illustrated below.
OSCI
OSCO
Fig. 6-17 External Clock Input Circuit
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 69
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-18 below depicts such a circuit. The same applies to the HXT1 mode, HTX2 mode, LXT1 mode and LXT2 mode.
C1 OSCI Crystal OSCO RS C2
Fig. 6-18 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each resonator has its own attribute, user should refer to the resonator specifications for the appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut crystal or low frequency mode. Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type Ceramic Resonators Frequency Mode HXT Frequency 455kHz 2.0 MHz 4.0 MHz 32.768kHz LXT Crystal Oscillator HXT 100kHz 200kHz 455kHz 1.0 MHz 2.0 MHz 4.0 MHz C1 (pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2 (pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15
70 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Circuit diagrams for serial and parallel modes Crystal/Resonator:
330 C 7404 7404 7404 330
OSCI
Crystal
Fig. 6-19 Serial Mode Crystal/Resonator Circuit Diagram
7404
4.7K
10K
V dd
O SC I
7404
10K
C rystal
10K
C1
C2
Fig. 6-20 Parallel Mode Crystal/Resonator Circuit Diagram
6.11.3 External RC Oscillator Mode
For some applications that do not require precise timing calculation, the RC oscillator (Fig. 6-21 at right) offers a costeffective solution. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to manufacturing process variations. In order to maintain a stable system frequency, the values of the Cext should be no less than 20pF, and that of Rext should be no greater than 1M. If the frequency cannot be kept within this range, the frequency can be affected easily by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator will become unstable because the NMOS cannot correctly discharge the capacitance current.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
Vcc Rext
OSCI
Cext
Fig. 6-21 External RC Oscillator Mode Circuit
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the PCB layout have certain effects on the system frequency. The RC Oscillator frequencies:
Cext Rext
3.3k 20 pF 5.1k 10k 100k 3.3k 100 pF 5.1k 10k 100k 3.3k 300 pF 5.1k 10k 100k
Average Fosc 5V, 25C
3.5 MHz 2.5 MHz 1.30 MHz 140 KHz 1.27 MHz 850kHz 450kHz 48kHz 560kHz 370kHz 196kHz 20kHz
Average Fosc 3V, 25C
3.2 MHz 2.3 MHz 1.25 MHz 140kHz 1.21 MHz 820kHz 450kHz 50kHz 540kHz 360kHz 192kHz 20kHz
Note: : Measured based on DIP packages.
2 3
1
: The values are for design reference only. : The frequency drift is 30%
6.11.4 Internal RC Oscillator Mode
The EM78P341N/342N/343N offers a versatile internal RC mode with default frequency value of 4MHz. Internal RC oscillator mode has other frequencies (1MHz, 8MHz, and 455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below describes the EM78P341N/342N/343N internal RC drift with voltage, temperature, and process variations. Internal RC Drift Rate (Ta=25C, VDD=5V 5%, VSS=0V)
Internal RC Frequency
4MHz 16MHz 1MHz 455MHz
Drift Rate Temperature (-40C ~+85C)
5% 5% 5% 5%
Voltage (2.3V~5.5V)
5% 5% 5% 5%
Process
4% 4% 4% 4%
Total
14% 14% 14% 14%
Theoretical values are for reference only. Actual values may vary depending on the actual process.
72 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.12 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply stabilizes in steady state. The EM78P341N/342N/343N POR voltage range is 1.55 ~ 1.7V. Under customer application, when power is switched OFF, Vdd must drop below 1.9V and remains at OFF state for 10s before power can be switched ON again. Subsequently, the EM78P341N/342N/343N will reset and work normally. The extra external reset circuit will work well if Vdd rises fast enough (50ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems.
6.12.1 Programmable WDT Time-out Period
The Option word (WDTPS) is used to define the WDT time-out period (18ms or 4.5ms ). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic resonators, the lower the operation frequency is, the longer is the required set-up time.
6 5
6.12.2 External Power-on Reset Circuit
The circuit shown in the following figure implements an external RC to produce a reset pulse. The pulse width (time constant) should be kept long enough to allow the Vdd to reach the minimum operating voltage. This circuit is used when the power supply has a slow power rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40 K. This way, the voltage at Pin /RESET is held below 0.2V. The diode (D) functions as a short circuit at power-down. The "C" capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
Vdd R D /RESET Rin C
Fig. 6-22 External Power-on Reset Circuit
5 6
VDD=5V, WDT time-out period = 16.5ms 30%. VDD=3V, WDT time-out period = 18ms 30%. VDD=5V, WDT time-out period = 4.2ms 30%. VDD=3V, WDT time-out period = 4.5ms 30%. * 73
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.12.3 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but the residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Fig. 6-23 and Fig. 6-24 show how to create a protection circuit against residual voltage.
Vdd 33K Q1 /RESET 100K 1N4684 10K
Vdd
Fig. 6-23 Residual Voltage Protection Circuit 1
Vdd R1 Q1 /RESET R3 R2
Vdd
Fig. 6-24 Residual Voltage Protection Circuit 2
74 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.13 Code Option
EM78P341N/342N/343N has two CODE option words and one Customer ID word that are not part of the normal program memory.
Word 0
Bit 12 ~ Bit 0
Word1
Bit 12 ~ Bit 0
Word 2
Bit12 ~ Bit 0
6.13.1 Code Option Register (Word 0)
Word 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
-
Bit 1
-
Bit 0
-
LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 HLP
Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits
LVR1, LVR0
11 10 01 00
VDD Reset Level
2.7V 3.5V 4.0V
VDD Release Level
2.9V 3.7V 4.2V
NA (Power-on Reset) (Default)
Bits 10~9 (TYPE1 ~ TYPE0): Type selection for EM78P343N or EM78P342N or EM78P341N or 108C.
TYPE 1, TYPE 0
00 01 10 11
VDD Reset Level
108C (8-pin) EM78P341N (14-pin) EM78P342N (18-pin) EM78P343N (Default) (20-pin)
Bit 8 (CLKS):
Instruction period option bit
0 = two oscillator periods 1 = four oscillator periods (default)
Refer to Section 6.15 for Instruction Set
Bit 7 (ENWDTB):
Watchdog timer enable bit
0 = Enable 1 = Disable (default)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 75
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bits 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Modes Selection bits
Oscillator Modes
ERC (External RC oscillator mode); P70/OSCO acts as P70 ERC (External RC oscillator mode); P70/OSCO acts as OSCO IRC (Internal RC oscillator mode); P70/OSCO acts as P70 IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO 3 LXT1 (Frequency range of XT mode is 1MHz ~ 100kHz) 3 HXT1 (Frequency range of XT mode is 20MHz ~ 6MHz) 3 LXT2 (Frequency range of XT mode is 32kHz) 3 HXT2 (Frequency range of XT mode is 6MHz ~ 1MHz) (default)
1 2 3
OSC2
0 0 0 0 1 1 1 1
OSC1
0 0 1 1 0 0 1 1
OSC0
0 1 0 1 0 1 0 1
1 1
2 2
In ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4. In IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4. In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot and should not be defined as normal I/O pins.
Bit 3 (HLP): Power consumption selection 0 = Low power consumption, applies to working frequency at 4MHz or below 4MHz 1 = High power consumption, applies to working frequency above 4MHz (Default) Bits 2 ~ 0: Not used (reserved)
6.13.2 Code Option Register (Word 1)
Word 1 Bit 12 Bit 11 Bit 10
- -
Bit 9
Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
C3 C2 C1 C0
Bit 0
JMPTS RCOUT NRHL NRE CYES
RCM1 RCM0
Bits 12~11: Not used, (reserved). These bits are set to "1" all the time. Bit 10 (JMPTS): Long Instruction enable 0 = Disable LCALL, LJMP instruction 1 = Enable LCALL, LJMP instruction.(default) Bit 8 (RCOUT): System clock output enable bit in IRC or ERC mode 0 = OSCO pin is open drain 1 = OSCO output system clock (default) Bit 8 (NRHL): Noise rejection high/low pulses define bit. INT pin is falling or rising edge trigger 0 = Pulses equal to 8/fc is regarded as signal 1 = Pulses equal to 32/fc is regarded as signal (default)
NOTE The noise rejection function is turned off under the LXT and sleep mode.
76 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 7 (NRE):
Noise rejection enable
0 = disable noise rejection 1 = enable noise rejection (default), but in Low Crystal oscillator (LXT) mode, the noise rejection circuit is always disabled. Bit 6 (CYES):
Instruction cycle selection bit
0 = one instruction cycle 1 = two instructions cycles (default) Bit 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode
C3, C2, C1, & C0 must be set to "1" only (auto-calibration).
Bit 1 & Bit 0 (RCM1, RCM0): RC mode selection bits
RCM 1
1 1 0 0
RCM 0
1 0 1 0
Frequency (MHz)
4(Default) 16 1 455kHz
6.13.3 Customer ID Register (Word 2)
Word 2 Bit 12 Bit 11 Bit 10 Bit 9
- - - -
Bit 8
RESETENB
Bit 7
-
Bit 6
WDTPS
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
x x x x x x
Bits 12 ~ 9: Not used (reserved). These bits are set to "1" all the time. Bit 8 (RESETENB): P71/RESET pin select bit 1 = P71 is general purpose input pin or open-drain for output
Port (default)
0 = P71 set to /RESET pin Bit 7: Not used (reserved). This bit is set to "1" all the time. Bit 6 (WDTPS):
WDT Time-out Period Selection bit
WDT Time
1 0
Watchdog Timer*
18 ms (Default) 4.5 ms
*Theoretical values, for reference only
Bits 5 ~ 0: Customer's ID code
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.14 Low Voltage Detector
During a power source unstable situation, like external power noise interference or EMS test condition, will cause the power to vibrate fiercely. At the time the Vdd is unsettled, it maybe below working voltage. When the system supply voltage Vdd is below the working voltage, the IC kernel must keep all register status automatically.
6.14.1 Low Voltage Reset
LVR property is setting at code option Word 0, Bit 10,9 detail operation mode as following :
Word 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
-
Bit 1
-
Bit 0
-
LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 HLP
Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits.
LVR1, LVR0
11 10 01 00
VDD Reset Level
2.7V 3.5V 4.0V
VDD Release Level
2.9V 3.7V 4.2V
NA (Power-on Reset)
6.14.2 Low Voltage Detector
LVD property is setting at Register detail operation mode as following:
6.14.2.1 IOCD1 (LVD Control Register)
Bit
EM78P342L/343L ICE342N
7
TYPE1
6
TYPE0
5
LVR1
4
LVR0
3
LVDIE LVDIE
2
LVDEN LVDEN
1
LVD1 LVD1
0
LVD0 LVD0
NOTE
IOCD1< 3 > register is both readable and writable Individual interrupt is enabled by setting its associated control bit in the IOCD1< 4 > to "1." Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 3 (LVDIE): Low voltage Detector interrupt enable bit. 0 = Disable Low voltage Detector interrupt 1 = Enable Low voltage Detector interrupt
When the detect low level voltage state is used to enter an interrupt vector or enter next instruction, the LVDIE bit must be set to "Enable".
78 * Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 2 (LVDEN): Low Voltage Detector Enable bit 0 = Low voltage detector disable 1 = Low voltage detector enable Bits 1~0 (LVD1:0): Low Voltage Detector level bits.
LVDEN
1 1 1 1 0
LVD1, LVD0
11 10 01 00 xx
LVD voltage Interrupt Level
Vdd 2.3V Vdd > 2.3V Vdd 3.3V Vdd > 3.3V Vdd 4.0V Vdd > 4.0V Vdd 4.5V Vdd > 4.5V NA
/LVD
0 1 0 1 0 1 0 1 0
6.14.2.2
Bit 7
/LVD
RE (Interrupt Status 2 & Wake-up Control Register)
Bit 6
LVDIF
Bit 5
ADIF
Bit 4
CMPIF
Bit 3
ADWE
Bit 2
CMPWE
Bit 1
ICWE
Bit 0
LVDWE
NOTE RE < 6, 5, 4 > can be cleared by instruction but cannot be set.
IOCE0 is the interrupt mask register. Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared.
0 = Low voltage is detected. 1 = Low voltage is not detected or LVD function is disabled. Bit 6 (LVDIF): Low Voltage Detector interrupt flag
LVDIF reset to "0" by software or hardware.
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit. 0 = Disable Low Voltage Detect wake-up. 1 = Enable Low Voltage Detect wake-up.
When the Low Voltage Detect is used to enter an interrupt vector or to wake up the IC from sleep with Low Voltage Detect running, the LVDWE bit must be set to "Enable".
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.14.3 Programming Process
Follow these steps to obtain data from the LVD: 1. Write to the two bits (LVD1: LVD0) on the LVDCR register to define the LVD level. 2. Set the LVDWE bit, if the wake-up function is employed. 3. Set the LVDIE bit, if the interrupt function is employed. 4. Write "ENI" instruction, if the interrupt function is employed. 5. Set LVDEN bit to 1 6. Write "SLEP" instruction or Polling /LVD bit. 7. Clear the interrupt flag bit (LVDIF) when Low Voltage Detector interrupt occurred. The internal LVD module uses the internal circuit, and when the code option is set to enable the LVD module, the current consumption will increase to about 5A. During sleep mode, the LVD module continues to operate. If the device voltage drops slowly and crosses the detect point, the LVDIF bit will be set and the device will wake up from Sleep mode. The LVD interrupt flag is still set as the prior status. When the system resets, the LVD flag will be cleared. Figure 6-25 shows the LVD module to detect the external voltage situation. When Vdd drops not below VLVD, LVDIF is kept at "0". When Vdd drops below VLVD, LVDIF is set to "1". If global ENI is enabled, LVDIF will be set to "1", the next instruction will branch to an interrupt vector. The LVD interrupt flag is cleared to "0" by software. When Vdds drops below VRESET and it is less than 80s, the system will keep all the register status and the system halts but oscillation is active. When Vdd drops below VRESET and it is more than 80s, a system reset will occur. Refer to Section 6.5.1 for detailed RESET description.
LVDIF is cleared by software
Vdd VLVD VRESET
LVDIF
Internal Reset
18ms LVR Voltage drop System occur reset Vdd < Vreset not longer than 80us, the system still keeps on operating
Fig. 6-25 LVD Waveform Situation
80 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.15 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of two oscillator periods), unless the program counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case, these instructions need one or two instruction cycles as determined by the Code Option Register CYES bit. In addition, the instruction set has the following features: 1. Every bit of any register can be set, cleared, or tested directly. 2. The I/O registers can be regarded as general registers. That is, the same instruction can operate on I/O registers. The following symbols are used in the Instruction Set table:
Convention: R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruction
0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0000 0001 0010 0011 0100 rrrr 0000 0001 0010
Hex
0000 0001 0002 0003 0004 000r 0010 0011 0012
Mnemonic
NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A
Operation
No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R A VR A A VR R
Status Affected
None C None T, P T, P 1 None None None None None None 1 None None Z Z Z, C, DC Z, C, DC Z Z Z Z
0 0000 0001 0011 0013 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0001 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 0100 rrrr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 81
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Binary Instruction
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
Hex
02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1EAK 1EBK 1Fkk
Mnemonic
AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k LCALL k LJMP k ADD A,k
Operation
A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1[SP], kPC kPC k+A A
Status Affected
Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C None None None None 2 None 3 None None None None None None Z Z Z None Z, C, DC None None Z, C, DC
0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0 0 0 0 0 0 0111 0111 0111 100b 101b 110b 111b 01rr 10rr 11rr bbrr bbrr bbrr bbrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 1000 kkkk k kkkk kkkk kkkk 1 1110 1000 kkkk k kkkk kkkk kkkk 1 1111 kkkk kkkk
Note:
1 2 3
This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only. This instruction is not recommended for RF operation. This instruction cannot operate under RF.
82 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
7
Absolute Maximum Ratings
Items
Temperature under bias Storage temperature Input voltage Output voltage Working Voltage Working Frequency -40C -65C Vss-0.3V Vss-0.3V 2.5V DC
Rating
to to to to to to 85C 150C Vdd+0.5V Vdd+0.5V 5.5V 20MHz
8
DC Electrical Characteristics
Ta=25 C, VDD=5.0V5%, VSS=0V
Parameter
Crystal: VDD to 5V Fxt Crystal: VDD to 3V ERC: VDD to 5V IRC: VDD to 5 V IRC:VDD to 5V IRC:VDD to 5V IRC:VDD to 5V IRC:VDD to 5V
Symbol
Condition
Two cycles with two clocks R: 5.1K, C: 100 pF 8MHz,4MHz, 1MHz, 455kHz RCM0:RCM1=1:1 RCM0:RCM1=1:0 RCM0:RCM1=0:1 RCM0:RCM1=0:0 OSCI in RC mode OSCI in RC mode VIN = VDD, VSS Ports 5, 6, 7 Ports 5, 6, 7 /RESET /RESET TCC, INT TCC, INT OSCI in crystal mode OSCI in crystal mode VOH = VDD-0.5V VOH = VDD-0.5V
Min
DC DC F30% F30% 3.84 7.68 0.96 436.8 - - -1 - - - - - - - - - - F
Typ
- - 830 4.0 8.0 1.0 455 3.5 1.5 0 3.75 1.25 2.0 1.0 3.75 1.25 3.5 1.5 -3.7 -10 8
Max
20 F30% F30% 4.16 8.32 1.06 473.2 - - 1 - - - - - - - - - -
Unit
MHz MHz kHz Hz MHz MHz MHz kHz V V A V V V V V V V V mA mA
IRC1 IRC2 IRC3 IRC4
Input High Threshold VIHRC Voltage (Schmitt Trigger ) VILRC IIL VIH1 VIL1 VIHT1 VILT1 VIHT2 VILT2 VIHX1 VILX1 IOH1 IOH2 Input Low Threshold Voltage (Schmitt Trigger ) Input Leakage Current for input pins Input High Voltage (Schmitt Trigger ) Input Low Voltage (Schmitt Trigger ) Input High Threshold Voltage (Schmitt Trigger ) Input Low Threshold Voltage (Schmitt Trigger ) Input High Threshold Voltage (Schmitt Trigger ) Input Low Threshold Voltage (Schmitt Trigger ) Clock Input High Voltage Clock Input Low Voltage Output High Voltage (Ports 5, P60~66,P70) Output High Voltage (IR OUT (Port 67))
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 83
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Symbol
IOL1 IOL2 IPH IPL ISB1 ISB2 ICC1
Parameter
Output Low Voltage (Ports 5, P60~66, P70) Output Low Voltage (IR OUT (Port 67)) Pull-high current Pull-low current Power down current Power down current
Condition
VOL = GND+0.5V VOL = GND+0.5V Pull-high active, input pin at VSS Pull-low active, input pin at Vdd All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled
Min
- - -70 35 - - -
Typ
10 15 -75 40 1.0 6.0 15
Max
- - -80 45 2.0 10 20
Unit
mA mA A A A A A
Operating supply current /RESET= 'High', Fosc=32kHz (Crystal type,CLKS="0"), output at two clocks (VDD to pin floating, WDT disabled 3V) Operating supply current /RESET= 'High', Fosc=32kHz (Crystal type,CLKS="0"), output at two clocks (VDD to pin floating, WDT enabled 3V) /RESET= 'High', Fosc=4MHz Operating supply current (Crystal type, CLKS="0"), output at two clocks pin floating, WDT enabled /RESET= 'High', Fosc=10MHz Operating supply current (Crystal type, CLKS="0"), output at two clocks pin floating, WDT enabled
ICC2
-
15
25
A
ICC3
-
1.9
2.2
mA
ICC4
-
3.0
3.5
mA
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical results at 25C. These data are for design reference only.
8.1 AD Converter Characteristics
Vdd=2.5V to 5.5V, Vss=0V, Ta=25C
Symbol
VAREF VASS VAI IAI1 Ivdd Ivref Ivdd IVref
Parameter
Condition
Min.
2.5 Vss VASS 750 -10 500 200 450 10 0 0 0
Typ.
- - - 850 0 600 250 550 11 4 0.5 4
Max.
Vdd Vss VAREF 1000 +10 820 300 650 - 8 0.9 8
Unit
V V V uA uA uA uA uA Bits LSB LSB LSB
Analog reference voltage VAREF - VASS 2.5V Analog input voltage Analog supply current - Vdd=VAREF=5.0V, VASS =0.0V (V referenced from Vdd) Vdd=VAREF=5.0V, VASS=0.0V (V referenced from VREF) Vdd=5.0V, OP used Output voltage swing 0.2V to 4.8V Vdd=VAREF=5.0V, VASS =0.0V Vdd = 2.5 to 5.5V Ta=25C Vdd = 2.5 to 5.5V Ta=25C Vdd=VAREF=5.0V, VASS =0.0V
IAI2
Analog supply current OP current Resolution Linearity error Differential nonlinear error Full scale error
IOP RN LN DNL FSE
84 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Symbol
OE ZAI TAD TCN ADIV ADOV ADSR PSR
Parameter
Offset error Recommended impedance of analog voltage source ADC clock period AD conversion time ADC OP input voltage range ADC OP output voltage swing ADC OP slew rate Power Supply Rejection
Condition
Vdd=VAREF=5.0V, VASS =0.0V - Vdd=VAREF=5.0V, VASS =0.0V Vdd=VAREF=5.0V, VASS =0.0V Vdd=VAREF=5.0V, VASS =0.0V Vdd=VAREF=5.0V, VASS =0.0V, RL=10K Vdd=VAREF=5.0V, VASS =0.0V Vdd=5.0V0.5V
Min.
0 0 4 15 0 0 4.7 0.1 0
Typ.
2 8 - - - 0.2 4.8 0.3 -
Max.
4 10 - 15 VAREF 0.3 5 - 2
Unit
LSB K us TAD V V V/us LSB
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. There is no current consumption when ADC is off other than minor leakage current. 3. AD conversion result will not decrease when an increase of input voltage and no missing code will result. 4. These parameters are subject to change without further notice.
8.2 Comparator (OP) Characteristics
Vdd = 5.0V, Vss=0V, Ta=25C
Symbol
SR IVR OVS Iop Ico PSR R Vs
Parameter
Slew rate Input voltage range Output voltage swing Supply current of OP Supply current of Comparator Power-supply Rejection Ration for OP Operating range
Condition
Vdd =5.0V, VSS =0.0V Vd =5.0V, VSS =0.0V, RL=10K
Min.
0.1 0 0 4.7 250
Typ.
0.2
Max.
5
Unit
V/us V V uA uA
0.2 4.8 350 300
0.3 5 500
Vdd= 5.0V, VSS =0.0V
50 2.5
60
70 5.5
dB V
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 85
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
8.3 Device Characteristics
The graphs below were derived based on a limited number of samples and they are provided for reference only. Hence, the device characteristic shown herein cannot be guaranteed as fully accurate. In these graphs, the data may be out of the specified operating warranted range.
IRC OSC Frequency (VDD=3V)
Frequency (MHz) .
Temperature oC
Fig. 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V
IRC OSC Frequency (VDD=5V)
Frequency (M Hz) .
Temperature ( )
Fig. 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V
86 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
9
AC Electrical Characteristic
Ta=-40 to 85 C, VDD=5V5%, VSS=0V
Symbol
Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Tdrc
Parameter
Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input time period Device reset hold time /RESET pulse width Watchdog timer duration Input pin setup time Input pin hold time Output pin delay time ERC delay time
Conditions
- Crystal type RC type - Ta = 25C Ta = 25C Ta = 25C - - Cload=20pF Ta = 25C
Min
45 100 500 (Tins+20)/N* 11.3 2000 11.3 - 15 45 1
Type
50 - - - 16.2 - 16.2 0 20 50 3
Max
55 DC DC - 21.6 - 21.6 - 25 55 5
Unit
% ns ns ns ms ns ms ns ns ns ns
Note:1. *N = selected prescaler ratio
2. Twdt1: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as set-up time (18ms). 3. Twdt2: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as set-up time (4.5ms). 4. These parameters are hypothetical (not tested) and are provided for design reference only. 5. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical results at 25C. These data are for design reference use only. 6. The Watchdog timer duration is determined by code option Word1 (WDTPS).
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 87
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V
0.75VDD 0.25VDD
TEST POINTS
0.75VDD 0.25VDD
GND+0.5V
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
88 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
APPENDIX A. Package Type
OTP MCU
EM78P341NP EM78P341NM EM78P342NP EM78P342NM EM78P343NP EM78P343NM EM78P343NKM
Package Type
DIP SOP DIP SOP DIP SOP SSOP
Pin Count
14 14 18 18 20 20 20
Package Size
300mil 150mil 300mil 300mil 300mil 300mil 209mil
B Packaging Configuration
B.1 14-Lead Plastic Dual in line (PDIP) 300 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 89
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.2 14-Lead Plastic Small Outline (SOP)
150 mil
90 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.3 18-Lead Plastic Dual in line (PDIP)
300 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 91
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.4 18-Lead Plastic Small Outline (SOP)
300 mil
92 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.5 20-Lead Plastic Shrink Small Outline (SSOP)
209 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 93
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.6 20-Lead Plastic Dual-in-line (PDIP)
300 mil
94 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.7 20-Lead Plastic Small Outline (SOPP)
300 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
* 95
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
C Quality Assurance and Reliability
Test Category
Solderability
Test Conditions
Solder temperature=245 5C, for 5 seconds up to the stopper using a rosin-type flux Step 1: TCT, 65C (15mins)~150C (15mins), 10 cycles Step 2: Bake at 125C, TD (durance)=24 hrs Step 3: Soak at 30C /60% TD (durance)=192 hrs
Remarks
-
Pre-condition
Step 4: IR flow 3 cycles (Pkg thickness 2.5mm or 3 Pkg volume 350mm ----225 5C) (Pkg thickness 2.5mm or 3 Pkg volume 350mm ----240 5C )
For SMD IC (such as SOP, QFP, SOJ, etc)
Temperature cycle test Pressure cooker test High temperature / High humidity test High-temperature storage life High-temperature operating life Latch-up ESD (HBM)
-65 (15mins)~150C (15mins), 200 cycles TA =121C, RH=100%, pressure=2 atm, TD (durance) = 96 hrs TA=85C , RH=85% TD (durance)=168 , 500 hrs
- - - - - - IP_ND,OP_ND,IO_ND IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD, IP_PS,OP_PS,IO_PS,
TA=150C, TD (durance)=500, 1000 hrs TA=125C, VCC=Max. operating voltage, TD (durance) =168, 500, 1000 hrs TA=25C, VCC=Max. operating voltage, 150mA/20V TA=25C, 3KV
ESD (MM)
TA=25C,
300V
VDD-VSS(+),VDD_VSS (-)mode
C.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a certain section of ROM, an internal recovery circuit is auto started. If a noise caused address error is detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will then continue to execute the next program.
96 *
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)

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